Table II offers a look at the two different modes of operation
and the difference in power consumption.
the conversion will terminate immediately, before all 12 bits
have been decided. This can be a very useful feature when
a resolution of 12 bits is not needed. An example would be
when the converter is being used to monitor an input voltage
until some condition is met. At that time, the full resolution
of the converter would then be used. Short-cycling the
conversion can result in a faster conversion rate or lower
power dissipation.
POWER WITH
POWER WITH
CLK = 8MHz
fSAMPLE
CLK = 16 • fSAMPLE
500kHz
250kHz
100kHz
11mW
10mW
9mW
11mW
7mW
4mW
There are several very important items shown in Figure 6.
The conversion currently in progress is terminated when
CONV is taken HIGH during the conversion and then taken
LOW prior to tCKCH before the start of the 13th clock cycle.
Note that if CONV goes LOW during the 13th clock cycle,
then the LSB-first mode will be entered (Figure 5). Also,
when CONV goes LOW, the DATA output immediately
transitions to high impedance. If the output bit that is present
during that clock period is needed, CONV must not go LOW
until the bit has been properly latched into the receiving
logic.
TABLE II. Power Consumption versus CLK Input.
LSB FIRST DATA TIMING
Figure 5 shows a method to transmit the digital result in a
least-significant bit (LSB) format. This mode is entered
when CONV is pulled HIGH during the conversion (before
the end of the 12th clock) and then pulled LOW during the
13th clock (when D0, the LSB, is being transmitted). The
next 11 clocks then repeat the serial data, but in an LSB first
format. The converter enters the power-down mode during
the 13th clock and resumes normal operation when CONV
goes HIGH.
DATA FORMAT
The ADS7834 output data is in straight binary format as
shown in Figure 7. This figure shows the ideal output code
for the given input voltage and does not include the effects
of offset, gain, or noise.
SHORT-CYCLE TIMING
The conversion currently in progress can be “short-cycled”
with the technique shown in Figure 6. This term means that
tCVL
(1)
CONV
tCVH
1
2
3
4
5
6
7
CLK
tCVDD
D11
(MSB)
DATA
D10
D9
D8
D7
D6
SAMPLE/HOLD
MODE
SAMPLE
HOLD
INTERNAL
CONVERSION
STATE
IDLE
CONVERSION IN PROGRESS
FULL POWER
IDLE
tCVPD
POWER MODE
LOW POWER
NOTE: (1) The conversion currently in progress can be stopped by pulling CONV LOW during the conversion. This must occur at
least tCKCS prior to the start of the 13th clock cycle. The DATA output pin will tri-state and the device will enter the power-down
mode when CONV is pulled LOW.
FIGURE 6. Short-cycle Timing.
®
11
ADS7834
BB [ BURR-BROWN CORPORATION ]
