PACKAGE/ORDERING INFORMATION
MAXIMUM
MAXIMUM
INTEGRAL DIFFERENTIAL
LINEARITY
ERROR
(LSB)
LINEARITY
ERROR
(LSB)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE-
LEAD
PACKAGE
DESIGNATOR(1)
PACKAGE
MARKING(2)
ORDERING
NUMBER(3)
TRANSPORT
MEDIA, QUANTITY
PRODUCT
ADS7834E
ADS7834E
ADS7834EB
ADS7834EB
ADS7834P
ADS7834PB
±2
"
N/S(3)
"
MSOP-8
DGK
–40°C to +85°C
C34
"
C34
ADS7834E/250
Tape and Reel, 250
"
"
DGK
"
P
"
"
ADS7834E/2K5 Tape and Reel, 2500
ADS7834EB/250 Tape and Reel, 250
ADS7834EB/2K5 Tape and Reel, 2500
ADS7834P
ADS7834PB
±1
"
±1
MSOP-8
–40°C to +85°C
"
"
"
"
±2
±1
N/S(3)
±1
Plastic DIP-8
–40°C to +85°C
ADS7834P
ADS7834PB
Rails
Rails
"
"
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. (2) Performance Grade information is marked on the
reel. (3) N/S = Not Specified, typical only. However, 12-Bits no missing codes is ensured over temperature.
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
+VCC to GND ............................................................................–0.3V to 6V
Analog Inputs to GND .............................................. –0.3V to (VCC + 0.3V)
Digital Inputs to GND ............................................... –0.3V to (VCC + 0.3V)
Power Dissipation .......................................................................... 325mW
Electrostatic discharge can cause damage ranging from
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ......................................... –40°C to +85°C
Storage Temperature Range .......................................... –65°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
performance degradation to complete device failure. Texas
Instruments recommends that all integrated circuits be handled
and stored using appropriate ESD protection methods.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. Exposure to absolute maximum condi-
tions for extended periods may affect device reliability.
PIN CONFIGURATION
Top View
VREF
+IN
1
2
3
4
8
7
6
5
+VCC
CLK
VREF
+IN
1
2
3
4
8
7
6
5
+VCC
CLK
ADS7834
ADS7834
–IN
DATA
CONV
–IN
DATA
CONV
GND
GND
Plastic Mini-DIP-8
MSOP-8
PIN ASSIGNMENTS
PIN
NAME
DESCRIPTION
1
2
3
4
5
VREF
+IN
Reference Output. Decouple to ground with a 0.1µF ceramic capacitor and a 2.2µF tantalum capacitor.
Noninverting Input.
–IN
Inverting Input. Connect to ground or to remote ground sense point.
Ground.
GND
CONV
Convert Input. Controls the sample/hold mode, start of conversion, start of serial data transfer, type of serial transfer, and power
down mode. See the Digital Interface section for more information.
6
DATA
Serial Data Output. The 12-bit conversion result is serially transmitted most significant bit first with each bit valid on the rising edge
of CLK. By properly controlling the CONV input, it is possibly to have the data transmitted least significant bit first. See the Digital
Interface section for more information.
7
8
CLK
Clock Input. Synchronizes the serial data transfer and determines conversion speed.
+VCC
Power Supply. Decouple to ground with a 0.1µF ceramic capacitor and a 10µF tantalum capacitor.
ADS7834
2
SBAS098A
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