periods, DOUT will output the conversion result, most signifi-
cant bit first. After the least significant bit (B0) has been
output, subsequent clocks will repeat the output data but in a
least significant bit first format.
SYMBOL
tSMPL
DESCRIPTION
Analog Input Sample Time
Conversion Time
MIN
TYP MAX
UNITS
1.5
2.0
Clk Cycles
Clk Cycles
kHz
tCONV
tCYC
12
75
0
Throughput Rate
tCSD
CS Falling to
DCLOCK LOW
ns
After the most significant bit (B11) has been repeated, DOUT
will tri-state. Subsequent clocks will have no effect on the
converter. A new conversion is initiated only when CS has
been taken HIGH and returned LOW.
tSUCS
thDO
tdDO
CS Falling to
DCLOCK Rising
30
15
ns
ns
ns
DCLOCK Falling to
Current DOUT Not Valid
DATA FORMAT
DCLOCK Falling to Next
DOUT Valid
130
200
The output data from the ADS7822 is in straight binary
format as shown in Table II. This table represents the ideal
output code for the given input voltage and does not include
the effects of offset, gain error, or noise.
tdis
ten
CS Rising to DOUT Tri-State
40
75
80
ns
ns
DCLOCK Falling to DOUT
Enabled
175
tf
tr
DOUT Fall Time
DOUT Rise Time
90
200
200
ns
ns
110
DESCRIPTION
ANALOG VALUE
VREF
TABLE I. Timing Specifications (VCC = 2.7V and above,
DIGITAL OUTPUT
STRAIGHT BINARY
Full Scale Range
–40°C to +85°C.
Least Significant
Bit (LSB)
VREF/4096
BINARY CODE
HEX CODE
FFF
A falling CS signal initiates the conversion and data transfer.
The first 1.5 to 2.0 clock periods of the conversion cycle are
used to sample the input signal. After the second falling
DCLOCK edge, DOUT is enabled and will output a LOW
value for one clock period. For the next 12 DCLOCK
Full Scale
Midscale
VREF –1 LSB
1111 1111 1111
1000 0000 0000
0111 1111 1111
0000 0000 0000
VREF/2
800
Midscale – 1 LSB
Zero
V
REF/2 – 1 LSB
0V
7FF
000
TABLE II. Ideal Input Voltages and Output Codes.
1.4V
VOH
3kΩ
DOUT
VOL
DOUT
Test Point
tr
tf
100pF
CLOAD
Voltage Waveforms for DOUT Rise and Fall Times, tr, tf
Load Circuit for tdDO, tr, and tf
Test Point
DCLOCK
VIL
VCC
tdis Waveform 2, ten
3kΩ
DOUT
tdDO
VOH
tdis Waveform 1
100pF
CLOAD
DOUT
VOL
thDO
Load Circuit for tdis and ten
Voltage Waveforms for DOUT Delay Times, tdDO
VIH
CS/SHDN
CS/SHDN
DCLOCK
1
2
DOUT
Waveform 1(1)
90%
10%
tdis
VOL
DOUT
B11
DOUT
Waveform 2(2)
ten
Voltage Waveforms for tdis
Voltage Waveforms for ten
NOTES: (1) Waveform 1 is for an output with internal conditions such that the output
is HIGH unless disabled by the output control. (2) Waveform 2 is for an output with
internal conditions such that the output is LOW unless disabled by the output control.
FIGURE 2. Timing Diagrams and Test Circuits for the Parameters in Table I.
9
®
ADS7822
BB [ BURR-BROWN CORPORATION ]
