PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
28
VDIG
VIN
AGND1
REF
27 VANA
26 BUSY
25 CS
CAP
AGND2
D11 (MSB)
D10
24 R/C
23 BYTE
22 DZ
ADS7820
D9
21 DZ
D8
20 DZ
D7 10
D6 11
19 DZ
18 D0 (LSB)
17 D1
D5 12
D4 13
16 D2
DGND 14
15 D3
PIN ASSIGNMENTS
PIN #
NAME
DESCRIPTION
1
2
3
VIN
AGND1
REF
Analog Input. Full-scale input range is 0 to +5V.
Analog Ground. Used internally as ground reference point.
Reference Input/Output. Outputs internal reference of +2.5V nominal. Can also be driven by external system reference. In both
cases, connect to ground with a 2.2µF Tantalum capacitor.
4
CAP
Reference Buffer Capacitor. 2.2µF Tantalum to ground.
5
AGND2
Analog Ground.
6
D11 (MSB) Data Bit 11. Most Significant Bit (MSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW.
7
D10
D9
Data Bit 10. Hi-Z state when CS is HIGH, or when R/C is LOW.
8
Data Bit 9. Hi-Z state when CS is HIGH, or when R/C is LOW.
9
D8
Data Bit 8. Hi-Z state when CS is HIGH, or when R/C is LOW.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
D7
Data Bit 7. Hi-Z state when CS is HIGH, or when R/C is LOW.
D6
Data Bit 6. Hi-Z state when CS is HIGH, or when R/C is LOW.
D5
Data Bit 5. Hi-Z state when CS is HIGH, or when R/C is LOW.
D4
Data Bit 4. Hi-Z state when CS is HIGH, or when R/C is LOW.
DGND
D3
Digital Ground.
Data Bit 3. Hi-Z state when CS is HIGH, or when R/C is LOW.
D2
Data Bit 2. Hi-Z state when CS is HIGH, or when R/C is LOW.
D1
Data Bit 1. Hi-Z state when CS is HIGH, or when R/C is LOW.
D0 (LSB)
DZ
Data Bit 0. Lease Significant Bit (LSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Zero. LOW when CS LOW and R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Zero. LOW when CS LOW and R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Zero. LOW when CS LOW and R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.
Data Zero. LOW when CS LOW and R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.
DZ
DZ
DZ
BYTE
Byte Select. With BYTE LOW, data will be output as indicated above, causing pin 6 (D11) to output the MSB, and pin 18 (D0) to
output the LSB. Pins 19 to 22 will output LOWs. With BYTE HIGH, the top and bottom 8 bits of data will be switched, so that pin 6
outputs data bit 3, pin 9 outputs data bit 0 (LSB), pin 10 to 13 output LOWs, pin 15 outputs data bit 11 (MSB) and pin 22 outputs
data bit 4.
24
25
26
R/C
CS
Read/Convert input. With CS LOW, a falling edge on R/C puts the internal sample/hold into the hold state and starts a conversion.
With CS LOW, a rising edge on R/C enables the output data bits.
Chip Select. Internally OR’d with R/C. With R/C LOW, a falling edge on CS will initiate a conversion. With R/C HIGH, a falling edge
on CS will enable the output data bits.
BUSY
Busy Output. Falls when a conversion is started, and remains LOW until the conversion is completed and the data is latched into the
output register. With CS LOW and R/C HIGH, output data will be valid when BUSY rises, so that the rising edge can be used to
latch the data. CS or R/C must be high when BUSY rises, or another conversion will start, without time for signal acquisition.
27
28
VANA
Analog Supply Input. Nominally +5V. Connect directly to pin 28. Decouple to ground with 0.1µF ceramic and 10µF Tantalum
capacitors.
VDIG
Digital Supply Input. Nominally +5V. Connect directly to pin 27. Must be ≤ VANA.
®
4
ADS7820
BB [ BURR-BROWN CORPORATION ]
