CAP
other CMOS A/D converters, releases 5%—10% of the
charge. There is also a resistive front end which attenuates
any charge which is released. The end result is a minimal
requirement for the op amp on the front end. Any op amp
sufficient for the signal in an application will be sufficient to
the drive the ADS7819.
CAP (pin 4) is the output of the internal reference buffer. A
10µF tantalum capacitor should be placed as close to the
CAP as possible to provide optimum switching currents for
the CDAC throughout the conversion cycle and compensa-
tion for the output of the buffer. Using a capacitor any
smaller than 1µF can cause the output buffer to oscillate and
may not have sufficient charge for the CDAC. Capacitor
values larger than 10µF will have little effect on improving
performance. The voltage on the CAP pin is approximately
2V when using the internal reference, or 80% of an exter-
nally supplied reference.
The resistive front end of the ADS7819 also provides a
guaranteed ±25V over voltage protection. In most cases, this
eliminates the need for external input protection circuitry.
INTERMEDIATE LATCHES
The ADS7819 does have 2tri-state outputs for the parallel
port, but intermediate latches should be used if the bus will
be active during conversions. If the bus is not active during
conversions, the tri-state outputs can be used to isolate the
A/D from other peripherals on the same bus.
LAYOUT
POWER
The ADS7819 uses the majority of its power for analog and
static circuitry, and it should be considered as an analog
component. For optimum performance, tie the analog and
digital +5V power pins to the same +5V power supply and
tie the analog and digital grounds together.
Intermediate latches are beneficial on any monolithic A/D
converter. The ADS7819 has an internal LSB size of 610µV.
Transients from fast switching signals on the parallel port,
even when the A/D is tri-stated, can be coupled through the
substrate to the analog circuitry causing degradation of
converter performance.
For best performance, the ±5V supplies can be produced
from whatever analog supply is used for the rest of the
analog signal conditioning. If ±12V or ±15V supplies are
present, simple regulators can be used. The +5V power for
the A/D should be separate from the +5V used for the
system’s digital logic. Connecting +VDIG (pin 27) directly to
a digital supply can reduce converter performance due to
switching noise from the digital logic.
Although it is not suggested, if the digital supply must be
used to power the converter, be sure to properly filter the
supply. Either using a filtered digital supply or a regulated
analog supply, both VDIG and VANA should be tied to the
same +5V source.
GROUNDING
Three ground pins are present on the ADS7819. DGND (pin 22)
is the digital supply ground. AGND2 (pin 5) is the analog
supply ground. AGND1 (pin 2) is the ground which all analog
signals internal to the A/D are referenced. AGND1 is more
susceptible to current induced voltage drops and must have the
path of least resistance back to the power supply.
All the ground pins of the ADS should be tied to the
analog ground plane, separated from the system’s digital
logic ground, to achieve optimum performance. Both ana-
log and digital ground planes should be tied to the “sys-
tem” ground as near to the power supplies as possible.
This helps to prevent dynamic digital ground currents
from modulating the analog ground through a common
impedance to power ground.
SIGNAL CONDITIONING
The FET switches used for the sample hold on many CMOS
A/D converters release a significant amount of charge injec-
tion which can cause the driving op amp to oscillate. The
FET switch on the ADS7819, compared to FET switches on
®
11
ADS7819
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