tCYC
CS/SHDN
DCLOCK
POWER
DOWN
tSUCS
tCSD
NULL
BIT
NULL
BIT
HI-Z
HI-Z
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0(1)
B11 B10 B9 B8
DOUT
(MSB)
tSMPL
tCONV
tDATA
Note: (1) After completing the data transfer, if further clocks are applied with CS
LOW, the A/D will output LSB-First data then followed with zeroes indefinitely.
tCYC
CS/SHDN
DCLOCK
DOUT
tSUCS
POWER DOWN
tCSD
NULL
HI-Z
HI-Z
BIT
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
(2)
(MSB)
tSMPL
tCONV
tDATA
Note: (2) After completing the data transfer, if further clocks are applied with CS
LOW, the A/D will output zeroes indefinitely.
t
DATA: During this time, the bias current and the comparator power down and the reference input
becomes a high impedance node, leaving the CLK running to clock out LSB-First data or zeroes.
FIGURE 4. ADS7817 Basic Timing Diagrams.
A falling CS signal initiates the conversion and data transfer.
The first 1.5 to 2.0 clock periods of the conversion cycle are
used to sample the input signal. After the second falling
DCLOCK edge, DOUT is enabled and will output a LOW
value for one clock period. For the next 12 DCLOCK
periods, DOUT will output the conversion result, most sig-
nificant bit first. After the least significant bit (B0) has been
output, subsequent clocks will repeat the output data but in
a least significant bit first format.
POWER DISSIPATION
The architecture of the converter, the semiconductor fabrica-
tion process, and a careful design allow the ADS7817 to
convert at up to a 200kHz rate while requiring very little
power. Still, for the absolute lowest power dissipation, there
are several things to keep in mind.
The power dissipation of the ADS7817 scales directly with
conversion rate. The first step to achieving the lowest power
dissipation is to find the lowest conversion rate that will
satisfy the requirements of the system.
After the most significant bit (B11) has been repeated, DOUT
will tri-state. Subsequent clocks will have no effect on the
converter. A new conversion is initiated only when CS has
been taken HIGH and returned LOW.
In addition, the ADS7817 is in power down mode under two
conditions: when the conversion is complete and whenever
CS is HIGH (see Figure 1). Ideally, each conversion should
occur as quickly as possible, preferably, at a 3.2MHz clock
rate. This way, the converter spends the longest possible
time in the power down mode. This is very important as the
converter not only uses power on each DCLOCK transition
(as is typical for digital CMOS components) but also uses
some current for the analog circuitry, such as the compara-
tor. The analog section dissipates power continuously, until
the power down mode is entered.
DATA FORMAT
The output data from the ADS7817 is in Binary Two’s
Complement format as shown in Table II. This table repre-
sents the ideal output code for the given input voltage and
does not include the effects of offset, gain error, or noise.
DESCRIPTION
ANALOG VALUE
2 • VREF
Figure 6 shows the current consumption of the ADS7817
versus sample rate. For this graph, the converter is clocked
at 3.2MHz regardless of the sample rate—CS is HIGH for
the remaining sample period. Figure 7 also shows current
consumption versus sample rate. However, in this case, the
DCLOCK period is 1/16th of the sample period—CS is
HIGH for one DCLOCK cycle out of every 16.
DIGITAL OUTPUT:
Full Scale Input Span
BINARY TWO’S COMPLEMENT
Least Significant
Bit (LSB)
2 • VREF/4096
BINARY CODE
0111 1111 1111
0000 0000 0000
1111 1111 1111
1000 0000 0000
HEX CODE
7FF
+Full Scale
Midscale
VREF –1 LSB
0V
000
Midscale – 1 LSB
–Full Scale
0V – 1 LSB
–VREF
FFF
800
TABLE II. Ideal Input Voltages and Output Codes.
®
ADS7817
10
BB [ BURR-BROWN CORPORATION ]
