converter not only uses power on each DCLOCK transition
(as is typical for digital CMOS components) but also uses
some current for the analog circuitry, such as the compara-
tor. The analog section dissipates power continuously, until
the power down mode is entered.
1000
100
10
Figure 3 shows the current consumption of the ADS7816
versus sample rate. For this graph, the converter is clocked
at 3.2MHz regardless of the sample rate—CS is HIGH for
the remaining sample period. Figure 4 also shows current
consumption versus sample rate. However, in this case, the
DCLOCK period is 1/16th of the sample period—CS is
HIGH for one DCLOCK cycle out of every 16.
TA = 25°C
VCC = VREF = +5V
fCLK = 3.2MHz
1
1
10
100
1000
There is an important distinction between the power down
mode that is entered after a conversion is complete and the
full power down mode which is enabled when CS is HIGH.
While both power down the analog section, the digital section
is powered down only when CS is HIGH. Thus, if CS is left
LOW at the end of a conversion and the converter is continu-
ally clocked, the power consumption will not be as low as
when CS is HIGH. See Figure 5 for more information.
Sample Rate (kHz)
FIGURE 3. Maintaining fCLK at the Highest Possible Rate
Allows Supply Current to Drop Directly with
Sample Rate.
1000
100
By lowering the reference voltage, the ADS7816 requires
less current to completely charge its internal capacitors on
both the analog input and the reference input. This reduction
in power dissipation should be weighed carefully against the
resulting increase in noise, offset, and gain error as outlined
in the Reference section. The power dissipation of the
ADS7816 is reduced roughly 10% when the reference volt-
age and input range are changed from 5V to 100mV.
10
TA = 25°C
VCC = VREF = +5V
fCLK = 16 • fSAMPLE
SHORT CYCLING
1
Another way of saving power is to utilize the CS signal to
short cycle the conversion. Because the ADS7816 places the
latest data bit on the DOUT line as it is generated, the
converter can easily be short cycled. This term means that
the conversion can be terminated at any time. For example,
if only 8-bits of the conversion result are needed, then the
conversion can be terminated (by pulling CS HIGH) after
the 8th bit has been clocked out.
1
10
100
1000
Sample Rate (kHz)
FIGURE 4. Scaling fCLK Reduces Supply Current Only
Slightly with Sample Rate.
60
This technique can be used to lower the power dissipation
(or to increase the conversion rate) in those applications
where an analog signal is being monitored until some con-
dition becomes true. For example, if the signal is outside a
predetermined range, the full 12-bit conversion result may
not be needed. If so, the conversion can be terminated after
the first n-bits, where n might be as low as 3 or 4. This
results in lower power dissipation in both the converter and
the rest of the system, as they spend more time in the power
down mode.
TA = 25°C
VCC = VREF = +5V
fCLK = 16 • fSAMPLE
50
CS LOW
(GND)
40
30
20
10
0
CS = HIGH (VCC
)
1
10
100
1000
Sample Rate (kHz)
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS7816 circuitry. This is particularly
true if the reference voltage is low and/or the conversion rate
is high. At 200kHz conversion rate, the ADS7816 makes a bit
decision every 312ns. That is, for each subsequent bit deci-
FIGURE 5. Shutdown Current is Considerably Lower with
CS HIGH than when CS is LOW.
®
11
ADS7816
BB [ BURR-BROWN CORPORATION ]
