1.4V
VOH
VOL
3kΩ
DOUT
DOUT
Test Point
tr
tf
100pF
CLOAD
Voltage Waveforms for DOUT Rise and Fall TImes tr, and tf
Load Circuit for tdDO, tr, and tf
Test Point
DCLOCK
VIL
VCC
tdDO
tdis Waveform 2, ten
3kΩ
DOUT
VOH
VOL
tdis Waveform 1
DOUT
100pF
CLOAD
thDO
Load Circuit for tdis and tden
Voltage Waveforms for DOUT Delay Times, tdDO
VIH
CS/SHDN
CS/SHDN
DCLOCK
DOUT
Waveform 1(1)
90%
10%
1
2
tdis
DOUT
Waveform 2(2)
VOL
DOUT
B11
ten
Voltage Waveforms for tdis
NOTES: (1) Waveform 1 is for an output with internal conditions such that
the output is HIGH unless disabled by the output control. (2) Waveform 2
is for an output with internal conditions such that the output is LOW unless
disabled by the output control.
Voltage Waveforms for ten
FIGURE 2. Timing Diagrams and Test Circuits for the Parameters in Table I.
DATA FORMAT
POWER DISSIPATION
The output data from the ADS7816 is in Straight Binary
format as shown in Table II. This table represents the ideal
output code for the given input voltage and does not include
the effects of offset, gain error, or noise.
The architecture of the converter, the semiconductor fabrica-
tion process, and a careful design allow the ADS7816 to
convert at up to a 200kHz rate while requiring very little
power. Still, for the absolute lowest power dissipation, there
are several things to keep in mind.
The power dissipation of the ADS7816 scales directly with
conversion rate. The first step to achieving the lowest power
dissipation is to find the lowest conversion rate that will
satisfy the requirements of the system.
DESCRIPTION
ANALOG VALUE
VREF
DIGITAL OUTPUT:
STRAIGHT BINARY
Full Scale Range
Least Significant
Bit (LSB)
VREF/4096
BINARY CODE
HEX CODE
In addition, the ADS7816 is in power down mode under two
conditions: when the conversion is complete and whenever
CS is HIGH (see Figure 1). Ideally, each conversion should
occur as quickly as possible, preferably, at a 3.2MHz clock
rate. This way, the converter spends the longest possible
time in the power down mode. This is very important as the
Full Scale
Midscale
VREF –1 LSB
VREF/2
1111 1111 1111
1000 0000 0000
0111 1111 1111
0000 0000 0000
FFF
800
7FF
000
Midscale – 1 LSB VREF/2 – 1 LSB
Zero 0V
Table II. Ideal Input Voltages and Output Codes.
®
ADS7816
10
BB [ BURR-BROWN CORPORATION ]
