the digital outputs tri-stating while the sample and hold
transitions to the hold mode. The change in digital outputs
results in noise being coupled onto the hold capacitor.
TIMING
The timing shown in Figure 2 and Table II is the recom-
mended method of operating the ADS7815. The falling edge
of CS initiates the conversion. During the conversion, the
digital outputs are tri-stated and BUSY is LOW. Near the
end of the conversion, the digital outputs become active with
the most recent conversion result. After a brief delay (see
time t11 in Figure 2 and Table II), BUSY rises. The rising
edge of BUSY is used to latch the digital result in Figure 1.
If a conversion is not in progress or is just about to finish, the
digital outputs will be active when R/C is HIGH and CS is
LOW. This is shown in Figure 2 and Figure 3. It is possible
to return CS HIGH during the initial part of the conversion
(as is done with R/C) and prevent the digital outputs from
becoming active. At a later time, the digital results could be
read by taking CS LOW. It is also possible to leave R/C
LOW, take CS HIGH during the conversion, and read the
results at a later time by taking R/C HIGH and CS LOW.
R/C AND CS
The R/C (read/convert) and CS signals control the start of
conversion and, when a conversion is not in progress, the
status of the digital outputs D15 through D0. It is possible to
start a conversion by taking CS LOW and then taking R/C
LOW. However, this is not recommended and will result in
a significant decrease in signal-to-noise ratio. This is due to
Following a conversion, if R/C and CS are both LOW 250ns
after BUSY rises, then a new conversion will be initiated
without allowing the proper acquisition period for the sample
and hold. R/C must remain HIGH or CS must be taken
HIGH within 250ns of BUSY rising.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t1
CS to R/C Delay
CS to BUSY Delay
Aperture Delay
200
ns
ns
ns
µs
ns
ns
ns
ns
µs
µs
ns
ns
t12
t2
40
40
R/C
t3
t4
BUSY LOW
3.3
t7
t8
t5
R/C LOW to CS LOW
BUSY HIGH to CS HIGH
Bus Access Time
100
t6
250
83
83
4
CS
t7
10
t8
Bus Relinquish Time
Throughput Time
DataValid
D15 - D0 Hi-Z State
MODE
Hi-Z State
t9
t10
t11
t12
Conversion Time
3.3
35
Acquire
Data Valid to BUSY HIGH
CS to R/C Setup Time
25
40
TABLE II. Conversion Timing.
FIGURE 3. Bus Timing.
t1
t5
R/C
t6
t9
CS
BUSY
t2
t4
t8
Hi-Z State
DataValid
t11
Hi-Z State
D15 - D0
t3
Convert
t10
Acquire
MODE
Acquire
FIGURE 2. ADS7815 Timing.
®
6
ADS7815
BB [ BURR-BROWN CORPORATION ]
