BASIC OPERATION
Figure 1 shows a basic circuit to operate the ADS7810.
Taking R/C (pin 23) LOW for a minimum of 40ns will
initiate a conversion. BUSY (pin 25) will go LOW and stay
LOW until the conversion is completed and the output
registers are updated. Data will be output in Binary Two’s
Complement with the MSB on D11 (pin 6). BUSY going
HIGH can be used to latch the data. All convert commands
will be ignored while BUSY is LOW.
The ADS7810 will begin tracking the input signal at the end
of the conversion. Allowing 1.25µs between convert com-
mands assures accurate acquisition of a new signal.
STARTING A CONVERSION
The combination of CS (pin 24) and R/C (pin 23) LOW for
a minimum of 40ns puts the sample/hold of the ADS7810 in
the hold state and starts a conversion. BUSY (pin 25) will go
LOW and stay LOW until the conversion is completed and
the internal output register has been updated. All new
convert commands during BUSY LOW will be ignored.
The ADS7810 will begin tracking the input signal at the end
of the conversion. Allowing 1.25µs between convert com-
mands assures accurate acquisition of a new signal. Refer to
Table I for a summary of CS, R/C, and BUSY states and
Figures 2 and 3 for timing parameters.
CS and R/C are internally OR’d and level triggered. There
is not a requirement which input goes LOW first when
initiating a conversion. If it is critical that CS or R/C initiate
the conversion, be sure the less critical input is LOW at least
10ns prior to the initiating input.
CS
1
↓
0
0
↓
↓
R/C
X
0
↓
1
1
1
BUSY
X
1
1
↑
1
0
OPERATION
None. Databus in Hi-Z state.
Initiates conversion. Databus remains in
Hi-Z state.
Initiates conversion. Databus enters Hi-Z
state.
Conversion completed. Valid data from
the most recent conversion on the databus.
Enables databus with valid data from the
most recent conversion.
Conversion in progress. Databus in Hi-Z
state, enabled when the conversion is
completed
Conversion in progress. Databus in Hi-Z
state, enabled when the conversion is
completed
Conversion completed. Valid data from the
most recent conversion in the output
register, but output pins D11-D0 are tri-stated.
New convert commands ignored. Conversion
in progress.
DESCRIPTION
Full Scale Range
Least Significant
Bit (LSB)
+Full Scale
(10V – 1LSB)
Midscale
One LSB below
Midscale
–Full Scale
ANALOG VALUE
±10V
4.88mV
DIGITAL OUTPUT
BINARY TWO'S COMPLEMENT
BINARY CODE
HEX CODE
7FF
000
FFF
800
9.995V
0V
–4.88mV
–10V
0111 1111 1111
0000 0000 0000
1111 1111 1111
1000 0000 0000
0
↑
0
0
0
↑
TABLE II. Ideal Input Voltages and Output Codes.
X
X
0
Table I. Control Line Functions for ‘read’ and ‘convert’.
0.1µF 10µF
+
+
1
2
3
0.1µF
D11 (MSB)
D10
D9
D8
D7
D6
D5
D4
10µF
+
4
5
6
7
ADS7810
8
9
10
11
12
13
14
21
20
19
18
17
16
15
NC
D0 (LSB)
D1
D2
D3
40ns min
28
27
26
25
24
23
22
Convert Pulse
0.1µF 10µF
+
+
BUSY
–5V
50Ω
±10V
+5V
FIGURE 1. Basic Operation
®
7
ADS7810
BURR-BROWN [ BURR-BROWN CORPORATION ]
