t
1
R/C
t
12
t
2
t
3
BUSY
t
4
t
5
t
6
MODE
Acquire
Convert
t
7
Acquire
t
8
Convert
DATA BUS
Data Valid
t
9
Hi-Z State
Data Valid
t
10
HI Z State
FIGURE 2. Conversion Timing with Outputs Enabled After Conversion (CS Tied Low).
t
11
R/C
t
1
CS
t
11
t
11
t
11
t
3
BUSY
t
4
t
5
t
6
MODE
Acquire
Convert
t
7
t
2
DATA
BUS
Hi-Z State
t
13
Data Valid
t
9
HI Z State
Acquire
FIGURE 3. Using CS to Control Conversion and Read Timing.
50Ω
V
IN
+5V
P
1
5kΩ
5V
–5V
P
2
5kΩ
0.1µF
10µF
+
AGND2
10µF
+
AGND2
NOTE: Use 1% metal film resistors. Trim offset at 0V first, then trim
gain at 10V.
V
IN
R
1
5kΩ
R
2
604kΩ
REF
V
IN
AGND1
50Ω
V
IN
AGND1
REF
CAP
0.1µF
CAP
FIGURE 4a. Circuit Diagram With External Hardware Trim.
FIGURE 4b. Circuit Diagram Without External Hardware
Trim.
®
9
ADS7810