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ADS7807U 参数 Datasheet PDF下载

ADS7807U图片预览
型号: ADS7807U
PDF下载: 下载PDF文件 查看货源
内容描述: 低功耗的16位采样CMOS模拟数字转换器 [Low-Power 16-Bit Sampling CMOS ANALOG-to-DIGITAL CONVERTER]
分类和应用: 转换器模数转换器光电二极管
文件页数/大小: 23 页 / 522 K
品牌: BB [ BURR-BROWN CORPORATION ]
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cycle. This capacitor also provides compensation for the  
output of the buffer. Using a capacitor any smaller than 1µF  
can cause the output buffer to oscillate and may not have  
sufficient charge for the CDAC. Capacitor values larger than  
2.2µF will have little affect on improving performance. See  
Figures 10 and 11.  
REFD  
REFD HIGH will power-down the internal 2.5V reference. All  
other analog circuitry, including the reference buffer, will be  
active. REFD should be HIGH when using an external  
reference to minimize power consumption and the loading  
effects on the external reference. See Figure 10 for the  
characteristic impedance of the reference buffers input for  
both REFD HIGH and LOW. The internal reference con-  
sumes approximately 5mW.  
7000  
6000  
5000  
4000  
3000  
2000  
1000  
0
LAYOUT  
POWER  
For optimum performance, tie the analog and digital power  
pins to the same +5V power supply and tie the analog and  
digital grounds together. As noted in the electrical character-  
istics, the ADS7807 uses 90% of its power for the analog  
circuitry. The ADS7807 should be considered as an analog  
component.  
0.1  
1
10  
100  
CAPPin Value (µF)  
The +5V power for the A/D converter should be separate  
from the +5V used for the systems digital logic. Connecting  
FIGURE 11. Power-Down to Power-Up Time vs Capacitor  
Value on CAP.  
VDIG (pin 28) directly to a digital supply can reduce converter  
performance due to switching noise from the digital logic. For  
best performance, the +5V supply can be produced from  
whatever analog supply is used for the rest of the analog  
signal conditioning. If +12V or +15V supplies are present, a  
simple +5V regulator can be used. Although it is not sug-  
gested, if the digital supply must be used to power the  
converter, be sure to properly filter the supply. Either using a  
filtered digital supply or a regulated analog supply, both VDIG  
and VANA should be tied to the same +5V source.  
The output of the buffer is capable of driving up to 1mA of  
current to a DC load. Using an external buffer will allow the  
internal reference to be used for larger DC loads and AC  
loads. Do not attempt to directly drive an AC load with the  
output voltage on CAP. This will cause performance degra-  
dation of the converter.  
REFERENCE  
AND POWER-DOWN  
GROUNDING  
Three ground pins are present on the ADS7807. DGND is the  
digital supply ground. AGND2 is the analog supply ground.  
The ADS7807 has analog power-down and reference power  
down capabilities via PWRD (pin 25) and REFD (pin 26),  
respectively. PWRD and REFD HIGH will power-down all  
analog circuitry maintaining data from the previous conver-  
sion in the internal registers, provided that the data has not  
already been shifted out through the serial port. Typical  
power consumption in this mode is 50µW. Power recovery is  
typically 1ms, using a 2.2µF capacitor connected to CAP.  
Figure 11 shows power-down to power-up recovery time  
relative to the capacitor value on CAP. With +5V applied to  
AGND1 is the ground to which all analog signals internal to the  
A/D converter are referenced. AGND1 is more susceptible to  
current induced voltage drops and must have the path of  
least resistance back to the power supply.  
All the ground pins of the A/D converter should be tied to an  
analog ground plane, separated from the systems digital  
logic ground, to achieve optimum performance. Both analog  
and digital ground planes should be tied to the system”  
ground as near to the power supplies as possible. This helps  
to prevent dynamic digital ground currents from modulating  
the analog ground through a common impedance to power  
ground.  
VDIG, the digital circuitry of the ADS7807 remains active at all  
times, regardless of PWRD and REFD states.  
PWRD  
PWRD HIGH will power-down all of the analog circuitry  
except for the reference. Data from the previous conversion  
will be maintained in the internal registers and can still be  
read. With PWRD HIGH, a convert command yields mean-  
ingless data.  
SIGNAL CONDITIONING  
The FET switches used for the sample hold on many CMOS  
A/D converters release a significant amount of charge injec-  
tion which can cause the driving op amp to oscillate. The  
ADS7807  
16  
SBAS022B  
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