INTERNAL DATA CLOCK
(During a Conversion)
SYMBOL
DESCRIPTION
MIN TYP MAX UNITS
t1
t2
t3
Convert Pulse Width
Data Valid Delay after R/C LOW
BUSY Delay from
0.04
12
20
85
µs
µs
ns
19
To use the internal data clock, tie EXT/INT (pin 8) LOW. The
combination of R/C (pin 22) and CS (pin 23) LOW will initiate
conversion ‘n’ and activate the internal data clock (typically
900kHz clock rate). The ADS7807 will output 16 bits of valid
data, MSB first, from conversion ‘n-1’ on SDATA (pin 19),
synchronized to 16 clock pulses output on DATACLK (pin 18).
The data will be valid on both the rising and falling edges of the
internal data clock. The rising edge of BUSY (pin 24) can be
used to latch the data. After the 16th clock pulse, DATACLK will
remain LOW until the next conversion is initiated, while SDATA
will go to whatever logic level was input on TAG (pin 20) during
the first clock pulse. Refer to Table VI and Figure 4.
Start of Conversion
t4
t5
BUSY LOW
19
90
20
µs
BUSY Delay after
ns
End of Conversion
t6
t7
Aperture Delay
40
19
ns
µs
µs
ns
ns
µs
Conversion Time
20
5
t8
Acquisition Time
t9
Bus Relinquish Time
BUSY Delay after Data Valid
Previous Data Valid
after Start of Conversion
Bus Access Time and BYTE Delay
Start of Conversion
10
20
12
83
t10
t11
60
19
t12
t13
83
ns
1.4
µs
to DATACLK Delay
EXTERNAL DATA CLOCK
t14
t15
DATACLK Period
1.1
75
µs
Data Valid to DATACLK
HIGH Delay
20
ns
To use an external data clock, tie EXT/INT (pin 8) HIGH. The
external data clock is not a conversion clock; it can only be
used as a data clock. To enable the output mode of the
ADS7807, CS (pin 23) must be LOW and R/C (pin 22) must
be HIGH. DATACLK must be HIGH for 20% to 70% of the
total data clock period; the clock rate can be between DC and
10MHz. Serial data from conversion ‘n’ can be output on
SDATA (pin 19) after conversion ‘n’ is completed or during
conversion ‘n + 1’.
t16
Data Valid after DATACLK
LOW Delay
400 600
ns
t17
t18
t19
t20
External DATACLK Period
External DATACLK LOW
External DATACLK HIGH
CS and R/C to External
DATACLK Setup Time
R/C to CS Setup Time
Valid Data after DATACLK HIGH
Throughput Time
100
40
ns
ns
ns
ns
50
25
t21
t22
10
25
ns
ns
µs
t7 + t8
25
An obvious way to simplify control of the converter is to tie
CS LOW and use R/C to initiate conversions.
TABLE VI. Conversion and Data Timing. TA = –40°C to +85°C.
While this is perfectly acceptable, there is a possible problem
when using an external data clock. At an indeterminate point
from 12µs after the start of conversion ‘n’ until BUSY rises,
the internal logic will shift the results of conversion ‘n’ into the
output register. If CS is LOW, R/C HIGH, and the external
clock is HIGH at this point, data will be lost. So, with CS
LOW, either R/C and/or DATACLK must be LOW during this
period to avoid losing valid data.
SERIAL OUTPUT
Data can be clocked out with the internal data clock or an
external data clock. When using serial output, be careful with
the parallel outputs, D7-D0 (pins 9-13 and 15-17), as these
pins will come out of Hi-Z state whenever CS (pin 23) is LOW
and R/C (pin 22) is HIGH. The serial output can not be tri-
stated and is always active. Refer to the Applications Infor-
mation section for specific serial interfaces.
t
7 + t8
CS or R/C(1)
t14
1
2
3
15
16
1
2
t13
DATACLK
t16
t15
MSB Valid
Bit 14 Valid
Bit 13 Valid
Bit 1 Valid
LSB Valid
MSB Valid
Bit 14 Valid
SDATA
BUSY
(Results from previous conversion.)
NOTE: (1) If controlling with CS, tie R/C LOW. Data bus pins will remain Hi-Z at all times.
If controlling with R/C, tie CS LOW. Data bus pins will be active when R/C is HIGH, and should be left unconnected.
FIGURE 4. Serial Data Timing Using Internal Data Clock (TAG tied LOW).
ADS7807
10
SBAS022B
www.ti.com
BB [ BURR-BROWN CORPORATION ]
