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ADS7804PB 参数 Datasheet PDF下载

ADS7804PB图片预览
型号: ADS7804PB
PDF下载: 下载PDF文件 查看货源
内容描述: 12位10ms的采样CMOS模拟数字转换器 [12-Bit 10ms Sampling CMOS ANALOG-to-DIGITAL CONVERTER]
分类和应用: 转换器模数转换器光电二极管
文件页数/大小: 10 页 / 185 K
品牌: BB [ BURR-BROWN CORPORATION ]
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DIGITAL  
I/O  
PIN #  
1
NAME  
VIN  
DESCRIPTION  
Analog Input. See Figure 7.  
2
AGND1  
REF  
CAP  
AGND2  
D15 (MSB)  
D14  
Analog Ground. Used internally as ground reference point.  
Reference Input/Output. 2.2µF tantalum capacitor to ground.  
Reference Buffer Capacitor. 2.2µF tantalum capacitor to ground.  
Analog Ground.  
3
4
5
6
O
O
O
O
O
O
O
O
Data Bit 11. Most Significant Bit (MSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW.  
Data Bit 10. Hi-Z state when CS is HIGH, or when R/C is LOW.  
Data Bit 9. Hi-Z state when CS is HIGH, or when R/C is LOW.  
Data Bit 8. Hi-Z state when CS is HIGH, or when R/C is LOW.  
Data Bit 7. Hi-Z state when CS is HIGH, or when R/C is LOW.  
Data Bit 6. Hi-Z state when CS is HIGH, or when R/C is LOW.  
Data Bit 5. Hi-Z state when CS is HIGH, or when R/C is LOW.  
Data Bit 4. Hi-Z state when CS is HIGH, or when R/C is LOW.  
Digital Ground.  
7
8
D13  
9
D12  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
D11  
D10  
D9  
D8  
DGND  
D7  
O
O
O
O
O
O
O
O
I
Data Bit 3. Hi-Z state when CS is HIGH, or when R/C is LOW.  
Data Bit 2. Hi-Z state when CS is HIGH, or when R/C is LOW.  
Data Bit 1. Hi-Z state when CS is HIGH, or when R/C is LOW.  
Data Bit 0. Lease Significant Bit (LSB) of conversion results. Hi-Z state when CS is HIGH, or when R/C is LOW.  
LOW when CS LOW, R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.  
LOW when CS LOW, R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.  
LOW when CS LOW, R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.  
LOW when CS LOW, R/C HIGH. Hi-Z state when CS is HIGH, or when R/C is LOW.  
Selects 8 most significant bits (LOW) or 8 least significant bits (HIGH).  
D6  
D5  
D4  
D3  
D2  
D1  
D0 (LSB)  
BYTE  
R/C  
I
With CS LOW and BUSY HIGH, a Falling Edge on R/C Initiates a New Conversion. With CS LOW, a rising edge on R/C  
enables the parallel output.  
25  
26  
CS  
I
Internally OR’d with R/C. If R/C LOW, a falling edge on CS initiates a new conversion.  
BUSY  
O
At the start of a conversion, BUSY goes LOW and stays LOW until the conversion is completed and the digital outputs  
have been updated.  
27  
28  
VANA  
VDIG  
Analog Supply Input. Nominally +5V. Decouple to ground with 0.1µF ceramic and 10µF tantalum capacitors.  
Digital Supply Input. Nominally +5V. Connect directly to pin 27. Must be VANA  
.
TABLE I. Pin Assignments.  
PIN CONFIGURATION  
CHARACTERIZATION CURVES  
Call factory for updated data sheet which includes character-  
VIN  
AGND1  
REF  
1
2
3
4
5
6
7
8
9
28 VDIG  
27 VANA  
26 BUSY  
25 CS  
ization curves.  
CAP  
AGND2  
D11 (MSB)  
D10  
24 R/C  
23 BYTE  
22 DZ  
ADS7804  
D9  
21 DZ  
D8  
20 DZ  
D7 10  
D6 11  
19 DZ  
18 D0 (LSB)  
17 D1  
D5 12  
D4 13  
16 D2  
DGND 14  
15 D3  
®
ADS7804  
4