PARALLEL OUTPUT (During a Conversion)
READING DATA
After conversion ‘n’ has been initiated, valid data from
conversion ‘n-1’ can be read and will be valid up to 16µs
after the start of conversion ‘n’. Do not attempt to read data
from 16µs after the start of conversion ‘n’ until BUSY (pin
26) goes HIGH; this may result in reading invalid data.
Refer to Table IV and Figures 3 and 5 for timing specifica-
tions.
The ADS7804 outputs full or byte-reading parallel data in
Binary Two’s Complement data output format. The parallel
output will be active when R/C (pin 24) is HIGH and CS
(pin 25) is LOW. Any other combination of CS and R/C will
tri-state the parallel output. Valid conversion data can be
read in a full parallel, 12-bit word or two 8-bit bytes on pins
6-13 and pins 15-22. BYTE (pin 23) can be toggled to read
both bytes within one conversion cycle. Refer to Table III
for ideal output codes and Figure 2 for bit locations relative
to the state of BYTE.
Note! For the best possible performance, data should not be
read during a conversion. The switching noise of the asyn-
chronous data transfer can cause digital feedthrough degrad-
ing the converter’s performance.
The number of control lines can be reduced by tieing CS
LOW while using R/C to initiate conversions and activate
the output mode of the converter. See Figure 3.
DIGITAL OUTPUT
BINARY TWO’S COMPLEMENT
DESCRIPTION
ANALOG INPUT
±10V
BINARY CODE
HEX CODE
Full Scale Range
Least Significant
Bit (LSB)
4.88mV
SYMBOL
DESCRIPTION
Convert Pulse Width
MIN TYP MAX UNITS
t1
t2
40
6000
8
ns
+Full Scale
(10V – 1LSB)
9.99512V
0111 1111 1111
7FF
Data Valid Delay after R/C LOW
µs
Midscale
0V
0000 0000 0000
1111 1111 1111
000
FFF
t3
t4
BUSY Delay from R/C LOW
BUSY LOW
65
8
ns
µs
One LSB below
Midscale
–4.88mV
t5
BUSY Delay after
End of Conversion
220
ns
–Full Scale
–10V
1000 0000 0000
800
t6
t7
Aperture Delay
Conversion Time
40
ns
µs
µs
ns
ns
µs
Table III. Ideal Input Voltages and Output Codes.
7.6
8
2
t8
Acquisition Time
PARALLEL OUTPUT (After a Conversion)
t9
Bus Relinquish Time
BUSY Delay after Data Valid
10
35
83
After conversion ‘n’ is completed and the output registers
have been updated, BUSY (pin 26) will go HIGH. Valid data
from conversion ‘n’ will be available on D11-D0 (pin 6-13
and 15-18 when BYTE is LOW). BUSY going HIGH can be
used to latch the data. Refer to Table IV and Figures 3 and
5 for timing specifications.
t10
t11
50 200
7.4
Previous Data Valid
after R/C LOW
t7 + t6
t12
Throughput Time
R/C to CS Setup Time
Time Between Conversions
9
10
83
µs
ns
µs
ns
10
t13
10
t14
Bus Access Time
and BYTE Delay
10
TABLE IV. Conversion Timing.
BYTE LOW
BYTE HIGH
+5V
6
7
23
22
21
20
19
18
17
16
15
6
7
23
22
21
20
19
18
17
16
15
Bit 11 (MSB)
Bit 10
Bit 9
Bit 3
Bit 2
LOW
LOW
LOW
LOW
Bit 0 (LSB)
Bit 1
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
ADS7804
ADS7804
8
8
Bit 1
9
9
Bit 8
Bit 0 (LSB)
LOW
10
11
12
13
14
10
11
12
13
14
Bit 7
Bit 6
LOW
Bit 5
LOW
Bit 4
Bit 2
LOW
Bit 10
Bit 11
Bit 3
FIGURE 2. Bit Locations Relative to State of BYTE (pin 23).
®
ADS7804
6
BB [ BURR-BROWN CORPORATION ]
