CS
1
R/C BUSY OPERATION
BASIC OPERATION
X
0
X
1
None. Databus is in Hi-Z state.
Figure 1 shows a basic circuit to operate the ADS7804 with
a full parallel data output. Taking R/C (pin 24) LOW for a
minimum of 40ns (6µs max) will initiate a conversion. BUSY
(pin 26) will go LOW and stay LOW until the conversion is
completed and the output registers are updated. Data will be
output in Binary Two’s Complement with the MSB on pin 6.
BUSY going HIGH can be used to latch the data. All convert
commands will be ignored while BUSY is LOW.
↓
Initiates conversion ‘n’. Databus remains
in Hi-Z state.
0
0
↓
↓
0
0
↓
1
1
1
↑
0
1
↑
1
0
0
↑
Initiates conversion ‘n’. Databus enters Hi-Z
state.
Conversion ‘n’ completed. Valid data from
conversion ‘n’ on the databus.
Enables databus with valid data from
conversion ‘n’.
Enables databus with valid data from
conversion ‘n-1’(1). Conversion n in process.
The ADS7804 will begin tracking the input signal at the end
of the conversion. Allowing 10µs between convert com-
mands assures accurate acquisition of a new signal.
Enables databus with valid data from
conversion ‘n-1’(1). Conversion ‘n’ in process.
New conversion initiated without acquisition
of a new signal. Data will be invalid. CS and/or
R/C must be HIGH when BUSY goes HIGH.
The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors compen-
sate for this adjustment and can be left out if the offset and gain
will be corrected in software (refer to the Calibration section).
X
X
0
New convert commands ignored. Conversion
‘n’ in process.
NOTE: (1) See Figures 2 and 3 for constraints on data valid from
conversion “n-1”.
STARTING A CONVERSION
Table II. Control Line Functions for Read and Convert.
The combination of CS (pin 25) and R/C (pin 24) LOW for a
minimum of 40ns immediately puts the sample/hold of the
ADS7804 in the hold state and starts conversion ‘n’. BUSY
(pin 26) will go LOW and stay LOW until conversion ‘n’ is
completed and the internal output register has been updated.
All new convert commands during BUSY LOW will be ig-
nored. CS and/or R/C must go HIGH before BUSY goes
HIGH or a new conversion will be initiated without sufficient
time to acquire a new signal.
CS and R/C are internally OR’d and level triggered. There is
not a requirement which input goes LOW first when initiating
a conversion. If, however, it is critical that CS or R/C initiates
conversion ‘n’, be sure the less critical input is LOW at least
10ns prior to the initiating input.
To reduce the number of control pins, CS can be tied LOW
using R/C to control the read and convert modes. This will
have no effect when using the internal data clock in the serial
output mode. However, the parallel output will become active
whenever R/C goes HIGH. Refer to the Reading Data sec-
tion.
The ADS7804 will begin tracking the input signal at the end
of the conversion. Allowing 10µs between convert com-
mands assures accurate acquisition of a new signal. Refer to
Table II for a summary of CS, R/C, and BUSY states and
Figures 3 through 5 for timing diagrams.
200Ω
1
28
+5V
2
27
26
25
24
23
22
21
20
19
18
17
16
15
+
+
33.2kΩ
2.2µF
0.1µF
10µF
+
3
BUSY
4
5
+
2.2µF
Convert Pulse
R/C
B11 (MSB)
6
B10
B9
B8
B7
B6
B5
B4
LOW
LOW
LOW
LOW
B0 (LSB)
B1
7
40ns min
6µs max
ADS7804
8
9
10
11
12
13
14
B2
B3
FIGURE 1. Basic Operation.
ADS7804
SBAS019A
5
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