PIN
FUNCTION
DESCRIPTION
D0
Mode Status
If LOW, Transparent Mode enabled for
data latches. If HIGH, latched Output
Mode enabled.
CS
t1
t2
t3
t6
D1
D2
CAL Flag
If HIGH, calibration cycle in progress.
WR
HBE
Pin 26 Status
If LOW, pin 26 used as input to initiate
calibration cycle. If HIGH, pin 26 used as
input to control sample-to-hold timing.
t5
D3
D4
D5
Power Down Status
If HIGH, in Power Down Mode.
Reserved for factory use.
SFR
VIH
VIL
POWER FAIL Flag
CAL ERROR Flag
BUSY Flag
If HIGH, a power supply failure has
occurred. (Supply fell below 3V.)
Valid Data
t16
D0 - D7
D6
D7
If HIGH, an overflow occurred during
calibration.
t17
If HIGH, conversion or calibration in
progress.
FIGURE 5. Writing to the SFR.
NOTE: These data are transferred to the bus when a read cycle is initiated
with SFR and HBE HIGH. Reading the SFR with SFR HIGH and HBE LOW
is reserved for factory use at this time, and will yield unpredictable data.
TABLE II. Reading the Special Function Register.
CS
RD
HBE
t8
t11
t10
t12
POWER DOWN MODE
Writing a HIGH to D3 in the SFR puts the ADS7803 in the
Power Down Mode. Power consumption is reduced to 50µW
and D3 remains HIGH. The internal clock and analog
circuitry are turned off, although the output registers and
SFR can still be accessed normally. To exit Power Down
Mode, either write a LOW to D3 in the SFR, or initiate a
calibration by sending a LOW to the CAL pin or writing
a HIGH to D1. Note that if the power supply falls below 3V
and then recovers, a calibration is automatically initiated,
and the SFR will be reset. D3 will be LOW, and the
ADS7803 will not be in the Power Down Mode.
t11
t12
SFR
VIH
t13
t14
SFR Data
D0 - D7
FIGURE 6. Reading the FSR.
SAMPLE/HOLD CONTROL MODE
With D2 in the SFR HIGH, a rising edge input on pin 26 will
switch the ADS7803 from sample-mode to hold-mode with
a 5ns aperture delay. This also initiates a conversion, which
will start within 1.5 CLK cycles.
During Power Down Mode, a pulse on CS and WR will
initiate a single conversion, then the ADS7803 will revert to
power down. Also, writing to D1 and D3 in the SFR will
initiate a calibration, do a single conversion and revert to the
Power Down Mode, in 185 clock cycles. Accurate conver-
sion results will be available in the output registers.
This mode allows full control over the sample-to-hold tim-
ing, which is especially useful where external events trigger
sampling timing.
The activation delay from power down to normal operation
is included in the sampling time. No extra time is required,
either when coming out of the Power Down Mode or when
making a single conversion in the Power Down Mode.
In the Sample/Hold Control Mode, pin 26 must be held
LOW a minimum of 2.5µs between conversions to allow
accurate acquisition of input signals. Also, offset error will
increase in this mode, since auto-zeroing of the comparator
is not synchronized to the sampling. Minimum offset is
achieved by synchronizing the sampling signal to CLK,
whether internal or external. Ideally, the sampling signal
OPERATION
CS/WR
SFR/HBE
D0
D1
D2
D3
D5
D4/D6/D7
Enables Transparent Mode for Data Latches
Enables Latched Output Mode for Data Latches
Initiates Calibration Cycle
LOW
LOW
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
HIGH(1)
X
X
X
X
X
X
LOW
LOW
LOW
LOW
LOW
LOW
X
X
X
X
X
X
HIGH
X
X
X
X
Activates Sample/Hold Control Mode
Activates Power Down Mode(2)
HIGH(1)
X
HIGH(1)
X
X
X
X
X
X
Resets Power Fail Flag
X
LOW
NOTES: (1) Writing a LOW here reactivates the standard mode of operation. (2) In Power Down Mode, a pulse on CS and WR will initiate a single conversion,
then the ADS7803 will revert to power down. (3) X means it can be either HIGH or LOW without affecting this action. Writing HIGH to D4 or D6, or writing with
SFR HIGH and HBE LOW, may result in unpredictable behavior. These modes are reserved for factory use at this time.
TABLE III. Writing to the Special Function Register.
®
9
ADS7803
BB [ BURR-BROWN CORPORATION ]
