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ADS7800AH 参数 Datasheet PDF下载

ADS7800AH图片预览
型号: ADS7800AH
PDF下载: 下载PDF文件 查看货源
内容描述: 12位3ms的采样模拟数字转换器 [12-Bit 3ms Sampling ANALOG-TO-DIGITAL CONVERTER]
分类和应用: 转换器模数转换器
文件页数/大小: 12 页 / 124 K
品牌: BB [ BURR-BROWN CORPORATION ]
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R/C  
tW  
tB  
BUSY  
tDBC  
tAP  
tDBE  
tAP  
Convert  
Converter  
Mode  
Acquire  
Convert  
tC  
Acquire  
tA  
tDD  
Hi-Z State  
tHDR and tHL  
Data  
BUS  
Data  
Valid  
Data  
Valid  
Hi-Z State  
Hi-Z State  
FIGURE 7. Read Mode: R/C Pulse HIGH— Outputs Enabled Only When R/C is High.  
SYMBOL  
PARAMETER  
MIN  
TYP  
MAX  
UNITS  
tW  
R/C Pulse Width  
BUSY delay from R/C  
40  
10  
80  
ns  
ns  
tDBC  
tB  
150  
2.7  
BUSY LOW  
2.5  
13  
µs  
tAP  
tAP  
tC  
Aperture Delay  
ns  
Aperture Jitter  
150  
2.47  
100  
75  
ps, rms  
µs  
Conversion Time  
2.70  
tDBE  
tDB  
tA  
BUSY from End of Conversion  
BUSY Delay after Data Valid  
Acquisition Time  
ns  
25  
200  
300  
3.0  
ns  
130  
2.6  
50  
ns  
tA+tC  
tHDR  
tS  
Throughput Time  
µs  
Valid Data Held After R/C LOW  
CS or HBE LOW before R/C Falls  
CS or HBE LOW after R/C Falls  
Data Valid from CS LOW, R/C HIGH, and HBE in Desired State (Load = 100pF)  
Valid Data Held After R/C Low  
Delay to Hi-Z State after R/C Falls or CS Rises (3kPullup or Pulldown)  
20  
25  
25  
ns  
5
ns  
tH  
0
ns  
tDD  
tHDR  
tHL  
65  
150  
150  
ns  
20  
50  
ns  
50  
ns  
TABLE III. Timing Specifications (TMIN to TMAX).  
Pin 24 may be slightly more sensitive than pin 23 to supply  
variations, but to maintain maximum system accuracy, both  
should be well isolated from digital supplies with wide load  
variations.  
tS  
tH  
CS or  
HBE  
To limit the effects of digital switching elsewhere in a  
system on the analog performance of the system, it often  
makes sense to run a separate +5V supply conductor from  
the supply regulator to any analog components requiring  
+5V, including the ADS7800.  
tW  
R/C  
tDBC  
BUSY  
The VS pins (23 and 24) should be connected together and  
bypassed with a parallel combination of a 6.8µF tantalum  
capacitor and a 0.1µF ceramic capacitor located close to the  
converter to obtain noise-free operation. (See Figure 2.) The  
–VS pin 22 should be bypassed with a 1µF tantalum  
capacitor, again as close as possible to the ADS7800.  
Data  
Bus  
Data Valid  
Hi-Z State  
tHDR and tHL  
FIGURE 8. Conversion Start Timing.  
Noise on the power supply lines can degrade converter  
performance, especially noise and spikes from a switching  
power supply. Appropriate supplies or filters must be used.  
The GND pins (4 and 13) are also separated internally, and  
should be directly connected to a ground plane under the  
®
10  
ADS7800