CS R/C HBE BUSY
OPERATION
R/C
1
0
0
X
1↓0
1
X
0
0
1
1
1
None - Outputs in Hi-Z State.
Holds Signal and Initiates Conversion.
Output Three-State Buffers Enabled once
Conversion has Finished.
tB
BUSY
0
0
0
X
1
1↓0
0
1
1
1
X
1
1
1
0
Enable Hi-Byte in 8-bit Bus Mode.
Inhibit Start of Conversion.
None - Outputs in Hi-Z State.
Conversion in Progress. Outputs Hi-Z
State. New Conversion Inhibited until
Present Conversion has Finished.
tDBC
tC
Converter Acquisition
Mode
X
Conversion
Acquisition
Conversion
tAP
Hold Time
TABLE II. Control Line Functions.
FIGURE 3. Acquisition and Conversion Timing.
For stand-alone operation, control of the ADS7800 is
accomplished by a single control line connected to R/C. In
this mode, CS and HBE are connected to GND. The output
data are presented as 12-bit words. The stand-alone mode
is used in systems containing dedicated input ports which
do not require full bus interface capability.
SYMBOL
PARAMETER
MIN
TYP MAX
UNITS
tDBC
tB
tAP
∆tAP
tC
BUSY delay from R/C
BUSY Low
Aperture Delay
Aperture Jitter
80
2.5
13
150
2.47 2.70
150
2.7
ns
µs
ns
ps, rms
µs
Conversion Time
Conversion is initiated by a HIGH-to-LOW transition on
R/C. The three-state data output buffers are enabled when
R/C is HIGH and BUSY is HIGH. Thus, there are two
possible modes of operation: conversion can be initiated
with either positive or negative pulses. In either case, the
R/C pulse must remain LOW a minimum of 40ns.
TABLE I. Acquisition and Conversion Timing.
For use with an 8-bit bus, the data can be read out in two
bytes under the control of pin 18, HBE. With a LOW input
on pin 18, at the end of a conversion, the 8 LSBs of data
are loaded into the latches on pins 9 through 12 and 14
through 17. Taking pin 18 HIGH then loads the 4 MSBs on
pins 14 through 17, with pins 9 through 12 being forced
LOW.
Figure 6 illustrates timing when conversion is initiated by
an R/C pulse which goes LOW and returns HIGH during the
conversion. In this case (Convert Mode), the three-state
outputs go into the Hi-Z state in response to the falling edge
of R/C, and are enabled for external access of the data after
completion of the conversion.
ANALOG INPUT RANGES
Figure 7 illustrates the timing when conversion is initiated
by a positive R/C pulse. In this mode (Read Mode), the
output data from the previous conversion is enabled during
the HIGH portion of R/C. A new conversion starts on the
falling edge of R/C, and the three-state outputs return to the
Hi-Z state until the next occurrence of a HIGH on R/C.
The ADS7800 offers two standard bipolar input ranges:
±10V and ±5V. If a ±10V range is required, the analog input
signal should be connected to pin 1. A signal requiring a
±5V range should be connected to pin 2. In either case, the
other pin of the two must be grounded or connected to the
adjustment circuits described in the section on calibration.
(See Figures 4 and 5, or 10 and 11.)
CONVERSION START
CONTROLLING THE ADS7800
A conversion is initiated on the ADS7800 only by a negative
transition occurring on R/C, as shown in Table I. No other
combination of states or transitions will initiate a conver-
sion. Conversion is inhibited if either CS or HBE are HIGH,
or if BUSY is LOW. CS and HBE should be stable a
minimum of 25ns prior to the transition on R/C. Timing
relationships for start of conversion are illustrated in Figure
8.
The ADS7800 can be easily interfaced to most micropro-
cessor-based and other digital systems. The microprocessor
may take full control of each conversion, or the ADS7800
may operate in a stand-alone mode, controlled only by the
R/C input. Full control consists of initiating the conversion
and reading the output data at user command, transmitting
data either all 12-bits in one parallel word, or in two 8-bit
bytes. The three control inputs (CS, R/C and HBE) are all
TTL/CMOS compatible. The functions of the control lines
are shown in Table II.
The BUSY output indicates the current state of the converter
by being LOW only during conversion. During this time the
three-state output buffers remain in a Hi-Z state, and
therefore data cannot be read during conversion. During this
period, additional transitions on the three digital inputs (CS,
R/C and HBE) will be ignored, so that conversion cannot
be prematurely terminated or restarted.
ADS7800
SBAS001A
7
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