tHRL
R/C
R/C
tHRH
tDS
tDS
STATUS
tCONVERSION
tDDR
tHDR
STATUS
tCONVERSION
tHDR
tHS
High-Z
DB11-DB0
High-Z-State
Data Valid
High-Z-State
DB11-DB0
Data Valid
Data Valid
FIGURE 3. R/C Pulse Low—OutputsEnabled AfterConver-
sion.
FIGURE 4. R/C Pulse High — Outputs Enabled Only While
R/C Is High.
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
tHRL
tDS
tHDR
tHRH
tDDR
Low R/C Pulse Width
STS Delay from R/C
Data Valid After R/C Low
High R/C Pulse Width
Data Access Time
25
ns
ns
ns
ns
ns
200
25
100
150
TABLE IV. Stand-Alone Mode Timing. (TA = TMIN to TMAX ).
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
Convert Mode
tDSC
STS delay from CE
CE Pulse width
CS to CE setup
CS low during CE high
R/C to CE setup
R/C low during CE high
AO to CE setup
60
30
20
20
0
200
ns
ns
ns
ns
ns
ns
ns
ns
tHEC
tSSC
tHSC
tSRC
tHRC
tSAC
tHAC
50
50
50
50
50
0
20
AO valid during CE high
50
20
Read Mode
tDD
Access time from CE
Data valid after CE low
Output float delay
CS to CE setup
R/C to CE setup
75
35
100
0
150
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHD
tHL
tSSR
tSRR
tSAR
tHSR
tHRR
tHAR
tHS
25
50
0
50
0
0
50
75
AO to CE setup
25
CS valid after CE low
R/C high after CE low
AO valid after CE low
STATUS delay after data valid
150
375
TABLE V. Timing Specifications, Fully Controlled Operation. (TA = TMIN to TMAX ).
CE
tHEC
CE
CS
tSSR
tHSR
tSSC
CS
tHRR
tHSC
R/C
R/C
tSSR
tHRC
tSRC
A
0
A
0
tSAC
tSAR
tHAR
Status
tHAC
tDSC
Status
tX*
tHS
tHD
High Impedance
DB11-DB0
DB11-DB0
High-Z
tDD
Data Valid
* tX includes tAQ + tC in ADC774 Emulation Mode,
tC only in S/H Control Mode.
tHL
FIGURE 5. Conversion Cycle Timing.
FIGURE 6. Read Cycle Timing.
®
9
ADS774
BB [ BURR-BROWN CORPORATION ]
