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SBAS308A− MAY 2004 − REVISED MARCH 2005
APPLICATION INFORMATION
latency of 16.5 clock cycles, after which the output data
is available as a 14-bit parallel word, coded in either
straight offset binary or binary two’s complement
format.
THEORY OF OPERATION
The ADS5542 is a low-power, 14-bit, 80MSPS, CMOS,
switched capacitor, pipeline ADC that operates from a
single 3.3V supply. The conversion process is initiated
by a falling edge of the external input clock. Once the
signal is captured by the input S&H, the input sample is
sequentially converted by a series of small resolution
stages, with the outputs combined in a digital correction
logic block. Both the rising and the falling clock edges
are used to propagate the sample through the pipeline
every half clock cycle. This process results in a data
INPUT CONFIGURATION
The analog input for the ADS5542 consists of a
differential sample-and-hold architecture implemented
using a switched capacitor technique, shown in
Figure 37.
S3a
L1
R1a
C1a
INP
S1a
CP1
CP3
R3
S2
CA
L2
R1b
C1b
S1b
VINCM
INM
1V
CP2
CP4
S3b
−
Ω−
L1, L2 : 6nH 10nH effective
Ω
8
R1a, R1b : 5
−
C
1a, C1b : 2.2pF 2.6pF
−
CP1, CP2 : 2.5pF 3.5pF
−
CP3, CP4, : 1.2pF 1.8pF
−
CA : 0.8pF 1.2pF
Ω
Ω
R3 : 80 to 120
Switches: S1a, S1b : On Resistance: 35
Ω−
Ω−
Ω
Ω
50
Ω
S2 : On Resistance: 7.5
S3a, S3b : On Resistance: 40
15
Ω−
60
Ω
All switches Off Resistance: 10G
:
NOTE All switches are ON during sampling phase, which is approximately one half of a clock period.
Figure 37. Analog Input Stage
20
BB [ BURR-BROWN CORPORATION ]
