ADS5510
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SLAS499–JANUARY 2007
SERIAL PROGRAMMING INTERFACE CHARACTERISTICS
The ADS5510 has a three-wire serial interface. The ADS5510 latches serial data SDATA on the falling edge of
serial clock SCLK when SEN is active.
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Serial shift of bits is enabled when SEN is low. SCLK shifts serial data at the falling edge.
Minimum width of data stream for a valid loading is 16 clocks.
Data is loaded at every 16th SCLK falling edge while SEN is low.
In case the word length exceeds a multiple of 16 bits, the excess bits are ignored.
Data can be loaded in multiples of 16-bit words within a single active SEN pulse.
The first 4-bit nibble is the address of the register while the last 12 bits are the register contents.
A3
A2
A1
A0
D11
D10
D9
D0
SDATA
ADDRESS
DATA
MSB
Figure 3. DATA Communication is 2-Byte, MSB First
t
SLOADS
t
SEN
SLOADH
t
t
t
SCLK
WSCLK WSCLK
SCLK
t
t
h(D)
su(D)
SDATA
MSB
LSB
MSB
LSB
16 x M
Figure 4. Serial Programming Interface Timing Diagram
Table 1. Serial Programming Interface Timing Characteristics
SYMBOL
tSCLK
PARAMETER
SCLK period
MIN(1)
TYP(1)
MAX(1)
UNIT
50
ns
tWSCLK
tSLOADS
tSLOADH
tDS
SCLK duty cycle
SEN to SCLK setup time
SCLK to SEN hold time
Data setup time
25%
50%
75%
8
6
8
6
ns
ns
ns
ns
tDH
Data hold time
(1) Typ, min, and max values are characterized, but not production tested.
8
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