ADS5510
www.ti.com
SLAS499–JANUARY 2007
APPLICATION INFORMATION
THEORY OF OPERATION
The ADS5510 is a low-power, 11-bit, 125 MSPS, CMOS, switched capacitor, pipeline ADC that operates from a
single 3.3-V supply. The conversion process is initiated by a falling edge of the external input clock. Once the
signal is captured by the input S&H, the input sample is sequentially converted by a series of small resolution
stages, with the outputs combined in a digital correction logic block. Both the rising and the falling clock edges
are used to propagate the sample through the pipeline every half clock cycle. This process results in a data
latency of 17.5 clock cycles, after which the output data is available as a 11-bit parallel word, coded in either
straight offset binary or binary two's complement format.
INPUT CONFIGURATION
The analog input for the ADS5510 consists of a differential sample-and-hold architecture implemented using the
switched capacitor technique shown in Figure 24.
S
3a
L1
R1a
C1a
INP
INM
S
S
1a
CP1
CP3
S
2
R3
CA
L2
R1b
C1b
VINCM
1V
1b
CP2
CP4
S
3b
L , L : 6 nH − 10 nH effective
1
2
R
1a
, R : 5W − 8W
1b
C , C : 2.2 pF − 2.6 pF
1a 1b
CP , CP : 2.5 pF − 3.5 pF
1
2
CP , CP : 1.2 pF − 1.8 pF
3
4
C : 0.8 pF − 1.2 pF
A
R : 80 W − 120 W
3
Swithches: S , S
On Resistance: 35 W − 50 W
1a 1b:
S : On Resistance: 7.5 W − 15 W
2
S
, S : On Resistance: 40 W − 60 W
3a 3b
All switches OFF Resistance: 10 GW
A. All Switches are ON in sampling phase which is approximately one half of a clock period.
Figure 24. Analog Input Stage
18
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