ADS5510
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SLAS499–JANUARY 2007
PIN CONFIGURATION (continued)
PIN ASSIGNMENTS(1)
TERMINAL
NO. OF
PINS
NAME
AVDD
NO.
I/O DESCRIPTION
5, 7, 9, 15, 22,
24, 26, 28, 33,
34, 37, 39
12
I
Analog power supply
6, 8, 12, 13,
14, 16, 18, 21,
23, 25, 27, 32,
36, 38
AGND
14
I
Analog ground
DRVDD
DRGND
49, 58
2
6
I
I
Output driver power supply
Output driver ground
1, 42, 48, 50,
57, 59
NC
44, 45, 46
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
—
I
Not connected
INP
19
20
29
30
31
17
35
41
40
10
11
4
Differential analog input (positive)
Differential analog input (negative)
INM
I
REFP
REFM
IREF
CM
O
O
I
Reference voltage (positive); 0.1-µF capacitor in series with a 1-Ω resistor to GND
Reference voltage (negative); 0.1-µF capacitor in series with a 1-Ω resistor to GND
Current set; 56-kΩ resistor to GND; do not connect capacitors
Common-mode output voltage
O
I
(2)
RESET
OE
Reset (active high), 200-kΩ resistor to AVDD
I
Output enable (active high)
DFS
I
Data format and clock out polarity select(3)(4)
Data converter differential input clock (positive)
Data converter differential input clock (negative)
Serial interface chip select(4)
Serial interface data(4)
Serial interface clock(4)
CLKP
CLKM
SEN
I
I
I
SDATA
SCLK
3
I
2
I
D0 (LSB) to
D10 (MSB)
47, 51-56,
60-63
11
O
11 bit parallel data output
OVR
64
43
1
1
O
O
Over-range indicator bit
CLKOUT
CMOS clock out in sync with data
(1) PowerPAD is connected to analog ground.
(2) If unused, the RESET pin should be tied to AGND. See the serial programming interface section for details.
(3) Table 3 defines the voltage levels for each mode selectable via the DFS pin.
(4) Pins OE, DFS, SEN, SDATA, and SCLK have internal clamping diodes to the DRVDD supply. Any external circuit driving these pins
must also run off the same supply voltage as DRVDD.
11
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