POWER DISSIPATION
OUTPUT ENABLE (OE
)
A majority of the ADS5421 total power consumption is used
for biasing, therefore; it is independent of the applied clock
frequency. Figure 14 shows the typical variation in power
consumption versus the clock speed. The current on the
VDRV supply is directly related to the capacitive loading of
the data output pins and care must be taken to minimize
such loading.
The digital outputs of the ADS5421 can be set to high
impedance (tri-state), exercising the output enable pin (OE).
For normal operation, this pin must be at a logic LOW
potential, whereas a logic HIGH voltage disables the outputs.
Even though this function affects the output driver stage, the
threshold voltages for the OE pin do not depend on the
output driver supply (VDRV), but are fixed (see the Electrical
Characteristics Table and the Digital Inputs Sections). Oper-
ating the OE function dynamically (e.g., high-speed multi-
plexing) should be avoided as it will corrupt the conversion
process.
45
FIN = 10MHz
40
35
30
25
20
15
POWER DOWN (PD)
A power-down pin is provided; when taken HIGH, this pin
shuts down portions within the ADS5421 and reduces the
power dissipation to less than 40mW. The remaining active
blocks include the internal reference, ensuring a fast reacti-
vation time. During power-down, data in the converter pipe-
line will be lost and new valid data will be subject to the
specified pipeline delay. If the PD pin is not used, it should
be tied to ground or a logic LOW level.
700
720
740
760
780
800
820
840
880
Power Dissipation (mW)
OUTPUT LOADING
It is recommended to keep the capacitive loading on the data
output lines as low as possible, preferably below 15pF.
Higher capacitive loading will cause larger dynamic currents
as the digital outputs are changing. For example, with a
typical output slew rate of 0.8V/ns and a total capacitive
loading of 10pF (including 4pF output capacitance, 5pF input
capacitance of external logic buffer, and 1pF PC board
parasitics), a bit transition can cause a dynamic current of
(10pF • 0.8V/1ns = 8mA). These high current surges can
feed back to the analog portion of the ADS5421 and ad-
versely affect the performance. If necessary, external buffers
or latches close to the converter’s output pins can be used to
minimize the capacitive loading. They also provide the added
benefit of isolating the ADS5421 from any digital activities on
the bus coupling back high-frequency noise.
FIGURE 14. Power Dissipation vs Clock Frequency.
DIGITAL OUTPUT DRIVER SUPPLY (VDRV)
A dedicated supply pin, VDRV, provides power to the logic
output drivers of the ADS5421 and can be operated with a
supply voltage in the range of +3.0V to +5.0V. This can
simplify interfacing to various logic families, in particular low-
voltage CMOS. It is recommended to operate the ADS5421
with a +3.3V supply voltage on VDRV. This will lower the
power dissipation in the output stages due to the lower output
swing and reduce current glitches on the supply line that may
affect the AC performance of the converter. The analog
supply (+VSA) and digital supply (+VSD) may be tied together,
with a ferrite bead or inductor between the supply pins. Each
of the these supply pins must be bypassed separately with at
least one 0.1µF ceramic chip capacitor, forming a pi-filter
(see Figure 15). The recommended operation for the ADS5421
is +5V for the +VS pins and +3.3V on the output driver pin
(VDRV).
POWER SUPPLIES
When defining the power supplies for the ADS5421, it is
highly recommended to consider linear supplies instead of
switching types. Even with good filtering, switching supplies
can radiate noise that could interfere with any high-
frequency input signal and cause unwanted modulation prod-
ucts. At its full conversion rate of 40MHz, the ADS5421
typically requires 170mA of supply current on the +5V sup-
plies. Note that this supply voltage should stay within a 5%
tolerance.
The configuration of the supplies requires that a specific
power-up sequence be followed for the ADS5421. Analog
voltage must be applied to the analog supply pin (+VSA
before applying a voltage to the driver supply (VDRV) or
before bringing both the digital supply (+VSD) and VDRV up
simultaneously. Powering up +VSD and VDRV prior to +VSA
will cause a large current on +VSA and result in the ADS5421
not functioning properly.
)
ADS5421
16
SBAS237D
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