ꢠ ꢃꢡ ꢢꢣ ꢤꢣ
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SBAS324 − JUNE 2004
PIN DESCRIPTIONS
NUMBER
OF PINS
NAME
PIN #
I/O
DESCRIPTION
AVDD
AVSS
LVDD
LVSS
1, 7, 14, 47, 54, 60, 63, 70, 75
9
14
2
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
I
Analog Power Supply
4, 8, 11, 50, 53, 57, 61, 62, 68, 72-74, 79, 80
Analog Ground
25, 35
I
LVDS Power Supply
15, 17, 18, 26, 36, 43, 44, 46
I
LVDS Ground
IN1
2
I
Channel 1 Differential Analog Input High
Channel 1 Differential Analog Input Low
Channel 2 Differential Analog Input High
Channel 2 Differential Analog Input Low
Channel 3 Differential Analog Input High
Channel 3 Differential Analog Input Low
Channel 4 Differential Analog Input High
Channel 4 Differential Analog Input Low
Channel 5 Differential Analog Input High
Channel 5 Differential Analog Input Low
Channel 6 Differential Analog Input High
Channel 6 Differential Analog Input Low
Channel 7 Differential Analog Input High
Channel 7 Differential Analog Input Low
Channel 8 Differential Analog Input High
Channel 8 Differential Analog Input Low
P
N
IN1
IN2
3
I
5
I
P
N
IN2
IN3
6
I
9
I
P
N
IN3
IN4
10
12
13
48
49
51
52
55
56
58
59
67
66
65
69
16
19
20
71
21
22
23
24
27
28
29
30
31
32
33
34
37
38
39
40
41
42
64
45
76
77
78
I
I
P
N
IN4
IN5
I
I
P
N
IN5
IN6
I
I
P
N
IN6
IN7
I
I
P
N
IN7
IN8
I
I
P
N
IN8
I
REF
I/O
I/O
O
I
Reference Top Voltage (0.1µF capacitor to ground)
Reference Bottom Voltage (0.1µF capacitor to ground)
Common-Mode Output Voltage
T
B
REF
V
CM
INT/EXT
PD
Internal/External Reference Select; 0 = External, 1 = Internal
Power-Down; 0 = Normal, 1 = Power-Down
Positive LVDS Clock
I
LCLK
O
O
I
P
LCLK
Negative LVDS Clock
N
ADCLK
Data Converter Clock Input
OUT1
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I/O
I
Channel 1 Positive LVDS Data Output
Channel 1 Negative LVDS Data Output
Channel 2 Positive LVDS Data Output
Channel 2 Negative LVDS Data Output
Channel 3 Positive LVDS Data Output
Channel 3 Negative LVDS Data Output
Channel 4 Positive LVDS Data Output
Channel 4 Negative LVDS Data Output
Channel 5 Positive LVDS Data Output
Channel 5 Negative LVDS Data Output
Channel 6 Positive LVDS Data Output
Channel 6 Negative LVDS Data Output
Channel 7 Positive LVDS Data Output
Channel 7 Negative LVDS Data Output
Channel 8 Positive LVDS Data Output
Channel 8 Negative LVDS Data Output
Positive LVDS ADC Clock Output
P
N
OUT1
OUT2
P
N
OUT2
OUT3
P
N
OUT3
OUT4
P
N
OUT4
OUT5
P
N
OUT5
OUT6
P
N
OUT6
OUT7
P
N
OUT7
OUT8
P
N
OUT8
ADCLK
P
ADCLK
Negative LVDS ADC Clock Output
Bias Current Setting Resistor of 56kΩ to Ground
Reset to Default; 0 = Reset, 1 = Normal
Chip Select; 0 = Select, 1 = No Select
Serial Data Input
N
ISET
RESET
CS
I
SDA
I
SCLK
I
Serial Data Clock
9
BB [ BURR-BROWN CORPORATION ]
