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SBAS295A–JULY 2004–REVISED JANUARY 2007
SERIAL INTERFACE TIMING
Outputs change on
next rising clock edge
after SEN goes high.
CLK
SEN
Start Sequence
t6
t1
t7
Data latched on
t2
each rising edge of SCLK.
SCLK
t3
D7
SDATA
D6
D5
D4
D3
D2
D1
D0
(MSB)
t4
t5
NOTE: Data is shifted in MSB first.
PARAMETER
DESCRIPTION
Serial CLK Period
MIN
50
20
20
5
TYP
MAX
UNIT
t1
t2
t3
t4
t5
t6
t7
ns
ns
ns
ns
ns
ns
ns
Serial CLK High Time
Serial CLK Low Time
Data Setup Time
Data Hold Time
5
SEN Fall to SCLK Rise
SCLK Rise to SEN Rise
8
8
8
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