TYPICAL CHARACTERISTICS: AVDD = 3.3V (Cont.)
TMIN = –40°C, TMAX = +85°C, typical values are at TA = +25°C, sampling rate = 40MSPS, 50% clock duty cycle, AVDD = 3.3V, DVDD = 3.3V, VDRV = 2.5V, –1dBFS,
DCA off, internal reference voltage, and 2VPP differential input, unless otherwise noted.
OUTPUT NOISE HISTOGRAM (DC Output)
60000
50000
40000
30000
20000
10000
0
N – 2
N – 1
N
N + 1
N + 2
Code
(3). When activated, this duty-cycle adjust circuit can accom-
modate for an incoming clock duty-cycle range of 35% to
65%, and re-time it to a 50% duty-cycle, which allows for
optimum internal clock timing. The ADS5220 has low power
dissipation in normal mode and has two power-down modes.
The device operates from a single +3.3V power supply and
has a separate digital output driver supply pin.
APPLICATION INFORMATION
THEORY OF OPERATION
The ADS5220 is a 12-bit, 40MSPS, CMOS ADC designed
with a fully differential pipeline architecture. The pipeline
consists of three sections: a 3-bit quantizer, eight middle
stages with a 1.5-bit quantizer for each stage, and a 4-bit
flash. The output of each pipeline stage is processed and
formed into 12-bit data in the digital error correction logic
section to ensure good differential linearity of the ADC. The
converter includes a high bandwidth track-and-hold amplifier
in the input stage as shown in Figure 1. The rising edge of
the input clock initiates the conversion process. Once the
signal is captured by the input track-and-hold, the bits are
sequentially encoded starting with the Most Significant Bit
(MSB). This process results in a data latency of 5 clock
cycles. The ADS5220 includes a high accuracy internal
reference and also allows the use of an external reference.
The input full-scale range is up to 2VPP and is selectable
based on the reference voltage setting. For normal opera-
tion, both analog inputs (IN, IN) require an external common-
mode voltage as a bias. The output data of the ADS5220 is
available as a 12-bit parallel word, either coded in a Straight
Offset Binary or Binary Two’s Complement format. The
ADS5220 includes an on-chip duty-cycle adjust (DCA)
circuit, controlled through the state of the Mode Select pin
S5
S3
VBIAS
CIN
CIN
S1
S2
IN
IN
T&H
S4
VBIAS
S6
Tracking Phase: S1, S2, S3, S4 closed; S5, S6 open
Hold Phase: S1, S2, S3, S4 open; S5, S6 closed
FIGURE1.SimplifiedCircuitofInputTrack-and-HoldAmplifier
of ADS5220.
ADS5220
SBAS261A
9
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