ADS1610
www.ti.com
SBAS344C–AUGUST 2005–REVISED OCTOBER 2006
Table 4. Four Modes of Operation(1)
Mode 1
Mode 0 OUTPUT RATE
OSR
6
SNR (TYP)
86dBFS
74dBFS
91dBFS
55dBFS
BITS
16
SETTLING TIME (DRDY cycles)
0
0
1
1
0
1
0
1
Default 10MHz mode
20MHz
55
25
55
NA
3
14
5MHz
12
1
16
60MHz bypass mode
12
(1) There is a pull-down resistor of 170kΩ on both mode pins; however, it is recommended that this pin be reduced to either high or low.
20MHz MODE
Table 5. Recommended RBIAS Resistor Values
In this mode, the oversampling ratio is three.
Decreasing the OSR from 6 to 3 doubles the data
rate, at the same time the performance is reduced
from 16 bits to 14 bits. Note that all 16 bits of DOUT
remain active in this mode. For fclk = 60MHz, the
data rate is 20MSPS. In addition, the group delay
becomes 1 µs or 13 DRDY cycles. In this mode the
noise increases. Typical SNR performance degrades
by 14dB. THD remains approximately the same.
for Different CLK Frequencies
fCLK
DATA
RATE
RBIAS
TYPICAL POWER
DISSIPATION
42MHz
48MHz
54MHz
60MHz
7MHz
8MHz
9MHz
10MHz
45kΩ
37kΩ
31kΩ
19kΩ
550mW
640mW
720mW
960mW
POWER-DOWN (PD)
5MHz MODE
When not in use, the ADS1610 can be powered
down by taking the PD pin low. There is an internal
pull-up resistor of 170kΩ on the PD pin, but it is
recommended that this pin be connected to DVDD if
not used. Once the PD pin is pulled high, allow at
least t11 (see Timing Specification Table) DRDY
cycles for the modulator and the digital filter to settle
before retrieving data.
In this mode the OSR is 12 for fclk = 60MHz and the
data rate in 5MSPS. Typical SNR performance
increases by 4dB. THD remains approximately the
same.
60MHz MODE
In this mode, decimation filters are bypassed. This
data output can be filtered externally by the user. For
fclk = 60MHz, the data rate is 60MSPS.
POWER SUPPLIES
Two supplies are used on the ADS1610: analog
(AVDD), and digital (DVDD). Each supply (other than
DVDD pins 49 and 50) must be suitably bypassed to
achieve the best performance. It is recommended
that a 1µF and 0.1µF ceramic capacitor be placed as
close to each supply pin as possible. Connect each
supply-pin bypass capacitor to the associated
ground, as shown in Figure 41. Each main supply
bus should also be bypassed with a bank of
capacitors from 47µF to 0.1µF, as shown in
Figure 41.
ANALOG POWER DISSIPATION
An external resistor connected between the RBIAS
pin and the analog ground sets the analog current
level, as shown in Figure 40. The current is inversely
proportional to the resistor value. Table 5 shows the
recommended values of RBIAS for different CLK
frequencies. Notice that the analog current can be
reduced when using a slower frequency CLK input
because the modulator has more time to settle.
Avoid adding any capacitance in parallel to RBIAS,
since this will interfere with the internal circuitry used
to set the biasing.
For optimum performance, insert a 10Ω resistor in
series with the AVDD2 supply (pin 58); the modulator
clocking circuitry. This resistor decouples switching.
ADS1610
RBIAS
RBIAS
AGND
Figure 40. External Resistor Used to Set
Analog Power Dissipation
19
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