ADS1610
www.ti.com
SBAS344C–AUGUST 2005–REVISED OCTOBER 2006
REFERENCE INPUTS (VREFN, VREFP, VMID)
Ω
392
The ADS1610 operates from an external voltage
reference. The reference voltage (Vref) is set by the
differential voltage between VREFN and VREFP: Vref
= (VREFP – VREFN). VREFP and VREFN each use
two pins, which should be shorted together. VMID,
approximately 2.5V, is used by the modulator. VCAP
connects to an internal node and must also be
bypassed with an external capacitor.
µ
0.001
F
ADS1610
VREFP
VREFP
OPA2822
µ
10
F
4V
µ
0.1
F
392Ω
0.1µF
0.001µF
µ
22 F
22µF
The voltages applied to these pins must be within the
values specified in the Electrical Characteristics
table. Typically VREFP = 4V, VMID = 2.5V, and
VREFN = 1V. The external circuitry must be capable
of providing both a DC and a transient current.
Figure 29 shows a simplified diagram of the internal
circuitry of the reference. As with the input circuitry,
switches S1 and S2 open and close as shown in
Figure 26.
VMID
OPA2822
10µF
2.5V
µ
0.1
F
Ω
392
0.001µF
µ
22
F
VREFN
VREFN
OPA2822
1V
µ
µ
µ
10
F
0.1
0.1
F
F
VCAP
ADS1610
AGND
S1
VREFP
VREFP
Figure 30. Recommended Reference
Buffer Circuit
Ω
300
50pF
VREFN
VREFN
S1
S2
CLOCK INPUT (CLK)
The ADS1610 uses an external clock signal to be
applied to the CLK input pin. The sampling of the
modulator is controlled by this clock signal. As with
any high-speed data converter, a high quality clock is
essential for optimum performance. Crystal clock
oscillators are the recommended CLK source; other
sources, such as frequency synthesizers may not be
adequate. Make sure to avoid excess ringing on the
CLK input; keeping the trace as short as possible will
help.
Figure 29. Conceptual Circuitry for the Reference
Inputs
Figure 30 shows the recommended circuitry for
driving these reference inputs. Keep the resistances
used in the buffer circuits low to prevent excessive
thermal noise from degrading performance. Layout of
these circuits is critical, make sure to follow good
high-speed layout practices. Place the buffers and
especially the bypass capacitors as close to the pins
as possible.
Measuring high-frequency, large-amplitude signals
requires tight control of clock jitter. The uncertainty
during sampling of the input from clock jitter limits the
maximum achievable SNR. This effect becomes
more pronounced with higher frequency and larger
magnitude inputs. The ADS1610 oversampling
topology reduces clock jitter sensitivity over that of
Nyquist rate converters like pipeline and successive
approximation converters by a factor of √6.
In order to not limit the ADS1610 SNR performance,
keep the jitter on the clock source below the values
shown in Table 1. When measuring lower frequency
and lower amplitude inputs, more CLK jitter can be
tolerated. In determining the allowable clock source
jitter, select the worst-case input (highest frequency,
largest amplitude) that will be seen in the application.
14
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