SPECIFICATIONS
At T
A
= T
MIN
to T
MAX
, +V
CC
= +5V, V
REF
= +5V, f
SAMPLE
= 12.5kHz, , f
CLK
= 16 • f
SAMPLE
, unless otherwise specified.
ADS1286, ADS1286A
PARAMETER
ANALOG INPUT
Full-Scale Input Range
Absolute Input Voltage
Capacitance
Leakage Current
SYSTEM PERFORMANCE
Resolution
No Missing Codes
Integral Linearity
Differential Linearity
Offset Error
Gain Error
Noise
Power Supply Rejection
SAMPLING DYNAMICS
Conversion Time
Acquisition Time
Small Signal Bandwidth
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion
SINAD
Spurious Free Dynamic Range
REFERENCE INPUT
REF Input Range
Input Resistance
Current Drain
V
IN
=
V
IN
=
V
IN
=
V
IN
=
5.0Vp-p
5.0Vp-p
5.0Vp-p
5.0Vp-p
at
at
at
at
1kHz
5kHz
1kHz
1kHz
1.25
CS = V
CC
CS = GND, f
CLK
= 0Hz
CS = V
CC
t
CYC
≥
640µs, f
CLK
≤
25kHz
t
CYC
= 80µs, f
CLK
= 200kHz
CONDITIONS
MIN
TYP
MAX
ADS1286K, ADS1286B
MIN
T
T
T
T
T
T
T
±1
±0.5
0.75
±2
50
82
±2
±1.0
±3
±8
T
T
T
T
T
T
T
±0.75
T
T
T
±0.5
±0.25
T
T
T
T
±1
±0.75
T
T
TYP
MAX
T
T
T
ADS1286C, ADS1286L
MIN
T
T
T
T
T
T
TYP
MAX
T
T
T
UNITS
+In – (–In)
+In
–In
0
–0.2
–0.2
25
±1
12
12
V
REF
V
CC
+0.2
+0.2
V
V
V
pF
µA
Bits
Bits
LSB
LSB
LSB
LSB
µVrms
dB
Clk Cycles
Clk Cycles
kHz
dB
dB
dB
dB
12
1.5
500
–85
–83
72
90
2.5
5000
5000
0.01
2.4
2.4
CMOS
I
IH
= +5µA
I
IL
= +5µA
I
OH
= 250µA
I
OL
= 250µA
3
0.0
3
0.0
Straight Binary
+V
CC
0.8
+V
CC
0.4
T
T
T
T
T
V
CC
+0.05V
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
2.5
20
20
T
T
T
T
T
T
V
MΩ
MΩ
µA
µA
µA
DIGITAL INPUT/OUTPUT
Logic Family
Logic Levels:
V
IH
V
IL
V
OH
V
OL
Data Format
T
T
T
T
V
V
V
V
POWER SUPPLY REQUIREMENTS
Power Supply Voltage
V
CC
Quiescent Current, V
ANA
t
CYC
≥
640µS, f
CLK
≤
25kHz
t
CYC
= 90µS, f
CLK
= 200kHz
Power Down
CS = V
CC
TEMPERATURE RANGE
Specified Performance
ADS1286, K, L
ADS1286A, B, C
+4.50
5
200
250
5.25
400
500
3
+70
+85
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
V
µA
µA
µA
°C
°C
0
–40
T
T
T
T
T
Specifications same as grade to the left.
TIMING CHARACTERISTICS
f
CLK
= 200kHz, T
A
= T
MIN
to T
MAX
.
SYMBOL
t
SMPL
t
SMPL (MAX)
t
CONV
t
dDO
t
dis
t
en
t
hDO
t
f
t
r
t
CSD
t
SUCS
PARAMETER
Analog Input Sample Time
Maximum Sampling Frequency
Conversion Time
Delay TIme, DCLOCK↓ to D
OUT
Data Valid
Delay TIme, CS↑ to D
OUT
Hi-Z
Delay TIme, DCLOCK↓ to D
OUT
Enable
Output Data Remains Valid After DCLOCK↓
D
OUT
Fall Time
D
OUT
Rise Time
Delay Time, CS↓ to DCLOCK↓
Delay Time, CS↓ to DCLOCK↑
®
CONDITIONS
See Operating Sequence
ADS1286
See Operating Sequence
See Test Circuits
See Test Circuits
See Test Circuits
C
LOAD
= 100pF
See Test Circuits
See Test Circuits
See Operating Sequence
See Operating Sequence
MIN
1.5
TYP
MAX
2.0
20
UNITS
Clk Cycles
kHz
Clk Cycles
ns
ns
ns
ns
ns
ns
ns
ns
15
12
85
25
50
30
70
60
150
50
100
100
100
0
30
ADS1286
2
BURR-BROWN [ BURR-BROWN CORPORATION ]
