ADS1274
ADS1278
www.ti.com
SBAS367–JUNE 2007
POWER-UP SEQUENCE
output, tie FORMAT[2:0], as shown in Figure 85.
DOUT[4:1]/[8:1] then becomes the modulator data
stream outputs for each channel and SCLK becomes
the modulator clock output. The DRDY/FSYNC pin
becomes an unused output and can be ignored. The
normal operation of the Frame-Sync and SPI
interfaces is disabled, and the functionality of SCLK
changes from an input to an output, as shown in
Figure 85.
The ADS1274/78 has three power supplies: AVDD,
DVDD, and IOVDD. AVDD is the analog supply that
powers the modulator, DVDD is the digital supply that
powers the digital core, and IOVDD is the digital I/O
power supply. The IOVDD and DVDD power supplies
can be tied together if desired (+1.8V). To achieve
rated performance, it is critical that the power
supplies are bypassed with 0.1μF and 10μF
capacitors placed as close as possible to the supply
pins. A single 10μF ceramic capacitor may be
substituted in place of the two capacitors.
Table 14. Modulator Output Clock Frequencies
MODULATOR
CLOCK
OUTPUT
(SCLK)
ADS1274 ADS1278
MODE
[1:0]
DVDD
(mA)
DVDD
(mA)
Figure 84 shows the power-up sequence of the
ADS1274/78. The power supplies can be sequenced
in any order. Each supply has an internal reset circuit
whose outputs are summed together to generate a
global power-on reset. After the supplies have
exceeded the reset thresholds, 218 fCLK cycles are
counted before the converter initiates the conversion
process. Following the CLK cycles, the data for 129
conversions are suppressed by the ADS1274/78 to
allow output of fully-settled data. In SPI protocol,
DRDY is held high during this interval. In frame-sync
protocol, DOUT is forced to zero. The power supplies
should be applied before any analog or digital pin is
driven. For consistent performance, assert SYNC
after device power-on when data first appear.
CLKDIV
00
01
1
1
1
0
1
0
fCLK/4
fCLK/4
fCLK/8
fCLK/4
fCLK/40
fCLK/8
4.5
4.0
2.5
2.5
1.0
0.5
8
7
4
4
1
1
10
11
Modulator Data Channel 1
Modulator Data Channel 2
DOUT1
DOUT2
IOVDD
DIN
FORMAT0
Modulator Data Channel 4/8(1)
Modulator Clock Output
FORMAT1 DOUT4/8(1)
AVDD
DVDD
3.0V nom(1)
1V nom(1)
1V nom(1)
FORMAT2
SCLK
NOTE: (1) ADS1274 has four channels; ADS1278 has eight channels.
IODVDD
Internal Reset
CLK
Figure 85. Modulator Output
218
fCLK
129 (max)
tDATA
In modulator output mode, the frequency of the
modulator clock output (SCLK) depends on the mode
selection of the ADS1274/78. Table 14 lists the
modulator clock output frequency and DVDD current
versus device mode.
DRDY
(SPI Protocol)
DOUT
(Frame-Sync Protocol)
Figure 86 shows the timing relationship of the
modulator clock and data outputs.
Valid Data
(1) The power-supply reset thresholds are approximate.
The data output is a modulated 1's density data
stream. When VIN = +VREF, the 1's density is
approximately 80% and when VIN = –VREF, the 1's
density is approximately 20%.
Figure 84. Power-Up Sequence
MODULATOR OUTPUT
The ADS1274/78 incorporates a 6th-order, single-bit,
chopper-stabilized modulator followed by
Modulator
SCLK
a
Clock Output
multi-stage digital filter that yields the conversion
results. The data stream output of the modulator is
available directly, bypassing the internal digital filter.
The digital filter is disabled, reducing the DVDD
current, as shown in Table 14. In this mode, an
external digital filter implemented in an ASIC, FPGA,
or similar device is required. To invoke the modulator
Modulator
DOUT
Data Output
(13ns max)
Figure 86. Modulator Output Timing
35
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