ADS1274
ADS1278
www.ti.com
SBAS367–JUNE 2007
TIMING CHARACTERISTICS: SPI FORMAT
tCLK
tCPW
CLK
· · ·
tCPW
tCD
tCONV
DRDY
tSD
tDS
tSCLK
tSPW
SCLK
tSPW
tDOPD
tMSBPD
tDOHD
Bit 23 (MSB)
Bit 22
tDIST
Bit 21
DOUT
DIN
tDIHD
TIMING REQUIREMENTS: SPI FORMAT
For TA = –40°C to +105°C, IOVDD = 1.65V to 3.6V, and DVDD = 1.65V to 1.95V.
SYMBOL
tCLK
PARAMETER
MIN
37
TYP
MAX
UNIT
ns
(1)
CLK period (1/fCLK
)
10,000
tCPW
CLK positive or negative pulse width
15
ns
(2)
tCONV
Conversion period (1/fDATA
)
256
2560
16
tCLK
ns
(3)
tCD
Falling edge of CLK to falling edge of DRDY
Falling edge of DRDY to rising edge of first SCLK to retrieve data
DRDY falling edge to DOUT MSB valid (propagation delay)
Falling edge of SCLK to rising edge of DRDY
SCLK period
22
18
(3)
tDS
1
tCLK
ns
tMSBPD
(3)
tSD
ns
(4)
tSCLK
1
0.4
10
tCLK
tCLK
ns
tSPW
SCLK positive or negative pulse width
(3)(5)
tDOHD
SCLK falling edge to new DOUT invalid (hold time)
SCLK falling edge to new DOUT valid (propagation delay)
New DIN valid to falling edge of SCLK (setup time)
Old DIN valid to falling edge of SCLK (hold time)
(3)
tDOPD
32
ns
tDIST
6
6
ns
(5)
tDIHD
ns
(1) fCLK = 27MHz maximum.
(2) Depends on MODE[1:0] and CLKDIV selection. See Table 6 (fCLK/fDATA).
(3) Load on DRDY and DOUT = 20pF.
(4) For best performance, limit fSCLK/fCLK to ratios of 1, 1/2, 1/4, 1/8, etc.
(5) tDOHD (DOUT hold time) and tDIHD (DIN hold time) are specified under opposite worst-case conditions (digital supply voltage and
ambient temperature). Under equal conditions, with DOUT connected directly to DIN, the timing margin is >4ns.
8
Copyright © 2007, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): ADS1274 ADS1278
BB [ BURR-BROWN CORPORATION ]
