ꢐ ꢕꢙ ꢚꢋ ꢛꢛ
ꢐ ꢕꢙ ꢚꢋ ꢛꢜ
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SBAS288D − JUNE 2003 − REVISED AUGUST 2004
The modulator measures the amplified differential input
signal, VIN = (AINP – AINN), against the differential
reference, VREF = (VREFP − VREFN). The differential
reference is scaled internally by a factor of two so that the
full-scale input range is 2VREF (for PGA = 1).
OVERVIEW
The ADS1255 and ADS1256 are very low-noise A/D
converters. The ADS1255 supports one differential or two
single-ended inputs and has two general-purpose digital
I/Os. The ADS1256 supports four differential or eight
single-ended inputs and has four general-purpose digital
I/Os. Otherwise, the two units are identical and are
referred to together in this data sheet as the ADS1255/6.
The digital filter receives the modulator signal and
provides a low-noise digital output. The data rate of the
filter is programmable from 2.5SPS to 30kSPS and allows
tradeoffs between resolution and speed.
Figure 5 shows a block diagram of the ADS1256. The
input multiplexer selects which input pins are connected to
the A/D converter. Selectable current sources within the
input multiplexer can check for open- or short-circuit
conditions on the external sensor. A selectable onboard
input buffer greatly reduces the input circuitry loading by
providing up to 80MΩ of impedance. A low-noise PGA
provides a gain of 1, 2, 4, 8, 16, 32, or 64. The ADS1255/6
converter is comprised of a 4th-order, delta-sigma
modulator followed by a programmable digital filter.
Communication is done over an SPI-compatible serial
interface with a set of simple commands providing control of
the ADS1255/6. Onboard registers store the various settings
for the input multiplexer, sensor detect current sources, input
buffer enable, PGA setting, data rate, etc. Either an external
crystal or clock oscillator can be used to provide the clock
source. General-purpose digital I/Os provide static read/write
control of up to four pins. One of the pins can also be used
to supply a programmable clock output.
VREFP VREFN
Σ
A/D
Converter
VREF
XTAL1/CLKIN
XTAL2
Clock
Generator
AIN0
AIN1
2
2VREF
AIN2
Input
AIN3
AIN4
AIN5
AIN6
AINP
AINN
Multiplexer
and
Sensor
Detect
•
VIN PGA
RESET
4th−Order
Modulator
PGA
1:64
Programmable
Digital Filter
Buffer
Σ
Control
SYNC/PDWN
AIN7
DRDY
SCLK
DIN
AINCOM
SPI
Serial
Interface
General
Purpose
Digital I/O
DOUT
CS
D3 D2
D1 D0/CLKOUT
ADS1256
Only
Figure 5. Block Diagram
11
BB [ BURR-BROWN CORPORATION ]
