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ADS1254E 参数 Datasheet PDF下载

ADS1254E图片预览
型号: ADS1254E
PDF下载: 下载PDF文件 查看货源
内容描述: 24位20kHz ,低功耗模拟数字转换器 [24-Bit, 20kHz, Low Power ANALOG-TO-DIGITAL CONVERTER]
分类和应用: 转换器
文件页数/大小: 17 页 / 281 K
品牌: BURR-BROWN [ BURR-BROWN CORPORATION ]
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ELECTRICAL CHARACTERISTICS
(Cont.)
All specifications at T
MIN
to T
MAX
, AV
DD
= +5V, DV
DD
= +1.8V. CLK = 8MHz, and V
REF
= 4.096, unless otherwise specified.
ADS1254E
PARAMETER
DIGITAL INPUT/OUTPUT
Logic Family
Logic Level: V
IH
V
IL
V
OH
V
OL
Input (SCLK, CLK, CHSEL0, CHSEL1) Hysteresis
Data Format
POWER-SUPPLY REQUIREMENTS
Power Supply Voltage
Quiescent Current
Operating Power
Power-Down Current
TEMPERATURE RANGE
Operating
Storage
–40
–60
CONDITIONS
MIN
TYP
MAX
UNITS
CMOS
0.65 • DV
DD
–0.3
DV
DD
–0.4
DV
DD
+ 0.3
0.35 • DV
DD
0.4
0.6
Offset Binary Two’s Complement
DV
DD
AV
DD
AV
DD
= +5V
DV
DD
= +1.8V
1.8
4.75
3.6
5.25
1.15
0.4
6.5
1
+85
+100
V
V
V
V
V
I
OH
= –500µA
I
OL
= 500µA
5
0.8
0.2
4.3
0.4
VDC
VDC
mA
mA
mW
µA
°C
°C
PIN CONFIGURATION
Top View
SSOP-20
PIN DESCRIPTIONS
PIN
1
2
3
4
5
NAME
CH1+
CH1–
CH2+
CH2–
CH3+
CH3–
AV
DD
CLK
PIN DESCRIPTION
Analog Input: Positive Input of the Differen-
tial Analog Input
Analog Input: Negative Input of the Differ-
ential Analog Input
Analog Input: Positive Input of the Differen-
tial Analog Input
Analog Input: Negative Input of the Differ-
ential Analog Input
Analog Input: Positive Input of the Differen-
tial Analog Input
Analog Input: Negative Input of the Differ-
ential Analog Input
Input: Analog Power Supply Voltage, +5V
Digital Input: Device System Clock. The
system clock is in the form of a CMOS-
compatible clock. This is a Schmitt-Trigger
input
Input: Digital Power Supply Voltage
No Connection
No Connection
Input: Digital Ground
Digital Output: Serial Data Output/Data
Ready. This output indicates that a new
output word is available from the ADS1254
data output register. The serial data is
clocked out of the serial data output shift
register using SCLK.
Digital Input: Serial Clock. The serial clock
is in the form of a CMOS-compatible clock.
The serial clock operates independently
from the system clock, therefore, it is pos-
sible to run SCLK at a higher frequency
than CLK. The normal state of SCLK is
LOW. Holding SCLK HIGH will either ini-
tiate a modulator reset for synchronizing
multiple converters or enter power-down
mode. This is a Schmitt-Trigger input.
Digital Input: Used to select analog input
channel. This is a Schmitt-Trigger Input
Digital Input: Used to select analog input
channel. This is a Schmitt-Trigger Input
Input: Analog Ground
Analog Input: Reference Voltage Input
Analog Input: Negative Input of the Differ-
ential Analog Input
Analog Input: Positive Input of the Differen-
tial Analog Input
CH1+
CH1–
CH2+
CH2–
CH3+
CH3–
AV
DD
CLK
1
2
3
4
5
6
7
8
20
19
CH4+
CH4–
6
7
8
18 V
REF
17 AGND
16
15
CHSEL0
CHSEL1
ADS1254E
9
10
11
12
13
DV
DD
NC
NC
DGND
DOUT/DRDY
14 SCLK
14
13 DOUT/DRDY
12 DGND
11 NC
SCLK
DV
DD
9
NC
10
15
16
17
18
19
20
CHSEL1
CHSEL0
AGND
V
REF
CH4–
CH4+
ADS1254
SBAS213
3