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ADS1234 参数 Datasheet PDF下载

ADS1234图片预览
型号: ADS1234
PDF下载: 下载PDF文件 查看货源
内容描述: 超低噪音,24位模拟数字转换器 [Ultra Low-Noise, 24-Bit Analog-to-Digital Converter]
分类和应用: 转换器
文件页数/大小: 10 页 / 163 K
品牌: BB [ BURR-BROWN CORPORATION ]
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ADS1232  
ADS1234  
www.ti.com  
SBAS350JUNE 2005  
ELECTRICAL CHARACTERISTICS: VREF = +5V  
All specifications TA = –40°C to +105°C, AVDD = DVDD = VREFP = +5V, VREFN = AGND, Internal Oscillator, SPEED =  
Low, Gain = 64 (unless otherwise specified).  
ADS1232, ADS1234  
PARAMETER  
Analog Inputs  
CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
Full-Scale Input Voltage  
(AINP - AINN)  
±0.5VREF/Gain  
V
V
AINxP or AINxN  
with respect to GND, Gain = 1  
AGND – 0.1  
AVDD + 0.1  
Common-mode Input Range  
Gain = 64, 128  
(0.5)AVDD – 1  
(0.5)AVDD + 1  
V
Gain = 1, 2  
500  
50  
nA  
nA  
Differential Input Current  
Gain = 64, 128  
System Performance  
Resolution  
No missing codes  
24  
TBD  
TBD  
Bits  
SPS  
Internal Oscillator, SPEED = High  
Internal Oscillator, SPEED = Low  
External Oscillator, SPEED = High  
External Oscillator, SPEED = Low  
Full Settling  
80  
TBD  
TBD  
10  
fCLK / 61440  
fCLK / 491520  
4
SPS  
Conversion Rate  
SPS  
SPS  
Digital Filter Settling Time  
Integral Non-Linearity (INL)  
Conversions  
Differential input, End point fit  
Gain = 1, 2  
±0.0002  
±0.0010  
±0.0015  
% of FSR(1)  
Differential input, End point fit  
Gain = 64, 128  
TBD  
% of FSR  
Gain = 1  
±0.2  
±2  
TBD  
TBD  
ppm of FS  
ppm of FS  
µV/°C  
nV/°C  
%
Input Offset Error(2)  
Input Offset Error Drift  
Gain Error(3)  
Gain = 64  
Gain = 1  
1
Gain = 64  
15  
Gain = 1  
0.001  
0.001  
0.5  
TBD  
TBD  
Gain = 64  
%
Gain = 1  
ppm/°C  
ppm/°C  
dB  
Gain Error Drift  
Gain = 64  
±4  
Internal oscillator, 50Hz and 60Hz  
100  
120  
110  
Normal-mode Rejection(4)  
External oscillator,  
50Hz and 60Hz, ±1Hz  
130  
dB  
at DC, Gain = 1, VDD = 1V  
TBD  
TBD  
100  
75  
dB  
dB  
Common-mode Rejection  
Input-Referred Noise  
at DC, Gain = 64, VDD = 0.1V  
See Noise Performance Tables  
at DC, Gain = 1, VDD = 1V  
TBD  
TBD  
100  
85  
dB  
dB  
Power-Supply Rejection  
at DC, Gain = 64, VDD = 0.1V  
Voltage Reference Input  
Voltage Reference Input  
VREF = VREFP - VREFN  
1
AGND – 0.1  
VREFN + 1.0  
AVDD AVDD + 0.1V  
VREFP – 1.0  
AVDD + 0.1  
50  
V
V
(VREF  
)
Negative Reference Input  
(VREFN)  
Positive Reference Input  
(VREFP)  
V
Voltage Reference  
Input Current  
nA  
(1) FSR = full scale range = VREF/Gain  
(2) Offset calibration can minimize these errors to the level of noise at any temperature.  
(3) Gain errors are calibrated at the factory (AVDD = +5V, all gains, TA = +25°C).  
(4) Specification is assured by the combination of design and final production test.  
3