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ADS1230IPW 参数 Datasheet PDF下载

ADS1230IPW图片预览
型号: ADS1230IPW
PDF下载: 下载PDF文件 查看货源
内容描述: 20位模拟数字转换器用于桥式传感器 [20-Bit Analog-to-Digital Converter For Bridge Sensors]
分类和应用: 转换器传感器
文件页数/大小: 25 页 / 502 K
品牌: BB [ BURR-BROWN CORPORATION ]
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ADS1230  
www.ti.com  
SBAS366OCTOBER 2006  
ELECTRICAL CHARACTERISTICS  
All specifications at TA = –40°C to +85°C, AVDD = DVDD = REFP = +5V, REFN = AGND, and Gain = 64, unless otherwise noted.  
ADS1230  
PARAMETER  
Analog Inputs  
CONDITIONS  
MIN  
TYP  
±0.5VREF/PGA  
±2  
MAX  
UNIT  
Full-Scale Input Voltage (AINP – AINN)  
Common-Mode Input Range  
Differential Input Current  
System Performance  
V
V
AGND + 1.5V  
AVDD – 1.5V  
nA  
Resolution  
No Missing Codes  
20  
69.5  
8.68  
Bits  
SPS  
Internal Oscillator, SPEED = High  
Internal Oscillator, SPEED = Low  
External Oscillator, SPEED = High  
External Oscillator, SPEED = Low  
Full Settling  
80  
86.4  
10.8  
10  
SPS  
Data Rate  
fCLK/61,440  
SPS  
fCLK/491,520  
SPS  
Digital Filter Settling Time  
Integral Nonlinearity (INL)  
4
±10  
±6  
Conversions  
ppm  
Differential Input, End-Point Fit, G = 64  
Differential Input, End-Point Fit, G = 128  
ppm  
Input Offset Error(1)  
Input Offset Drift  
Gain Error  
±3  
ppm of FS  
nV/°C  
%
±10  
±0.8  
±4  
Gain Drift  
ppm/°C  
dB  
Internal Oscillator, fDATA = 10SPS  
90  
Normal-Mode Rejection(2)  
External Oscillator, fDATA = 10SPS  
fIN = 50Hz or 60Hz, ±1Hz  
100  
dB  
Common-Mode Rejection  
Input-Referred Noise  
at DC, VDD = 0.1V  
fDATA = 10SPS  
110  
53  
dB  
nV, rms  
nV, rms  
dB  
fDATA = 80SPS  
100  
100  
Power-Supply Rejection  
at DC, VDD = 0.1V  
90  
Voltage Reference Input  
Voltage Reference Input (VREF  
)
VREF = REFP – REFN  
1.5  
AGND – 0.1  
REFN + 1.5  
AVDD  
10  
AVDD + 0.1V  
REFP – 1.5  
AVDD + 0.1  
V
V
Negative Reference Input (REFN)  
Positive Reference Input (REFP)  
Voltage Reference Input Current  
Digital  
V
nA  
All digital inputs except CLKIN  
CLKIN  
0.7 DVDD  
0.7 DVDD  
DGND  
DVDD + 0.1  
5.1  
V
V
VIH  
Logic Levels  
VIL  
0.2 DVDD  
V
VOH  
VOL  
IOH = 1mA  
DVDD – 0.4  
V
IOL = 1mA  
0.2 DVDD  
V
Input Leakage  
0 < VIN < DVDD  
±10  
6
µA  
MHz  
MHz  
External Clock Input Frequency (fCLKIN  
)
0.2  
4.9152  
Serial Clock Input Frequency (fSCLK  
)
5
(1) Offset calibration can minimize these errors to the level of noise at any temperature.  
(2) Specification is assured by the combination of design and final production test.  
3
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