ADS1230
www.ti.com
SBAS366–OCTOBER 2006
STANDBY MODE
When tSTANDBY has passed with SCLK held high,
Standby mode activates. DRDY/DOUT stays high
when Standby mode begins. SCLK must remain high
to stay in Standby mode. To exit Standby mode
(wakeup), set SCLK low. The first data after exiting
Standby mode is valid.
Standby mode dramatically reduces power
consumption by shutting down most of the circuitry.
In Standby mode, the entire analog circuitry is
powered down and only the clock source circuitry is
awake to reduce the wake-up time from the Standby
mode. To enter Standby mode, simply hold SCLK
high after DRDY/DOUT goes low; see Figure 28.
Standby mode can be initiated at any time during
readback; it is not necessary to retrieve all 20 bits of
data beforehand.
Data Ready
Standby Mode
DRDY/DOUT
SCLK
19
18
17
0
19
Start Conversion
1
20
tDSS
tSTANDBY
tS_RDY
Figure 28. Standby Mode Timing (can be used for single conversions)
SYMBOL
DESCRIPTION
MIN
0
MAX
12.44
99.94
UNITS
ms
SPEED = 1
SPEED = 0
SPEED = 1
SPEED = 0
SPEED = 1
SPEED = 0
SCLK high after DRDY/DOUT goes
low to activate Standby mode
(1)
tDSS
0
ms
20
µs
(1)
tSTANDBY
Standby mode activation time
20
µs
52.51
401.8
52.51
401.8
ms
(1)
tS_RDY
Data ready after exiting Standby mode
ms
(1) Value given for fCLK = 4.9152MHz. For different fCLK frequencies, scale proportional to CLK period. Expect a ±3% variation when an
internal oscillator is used.
17
Submit Documentation Feedback
BB [ BURR-BROWN CORPORATION ]
