SOURCE CURRENT
–40°C
A
IN3N
AIN3P
30
25
20
15
10
5
+5V
AIN2P
AIN2N
AIN1P
AIN1N
AGND
VBIAS
CS
AIN4N
AIN4P
REFIN
REFOUT
AVDD
R1
49.9kΩ
25°C
85°C
REF1004
+2.5V
1.0µF
+5V
AVDD
+5V
ADS1213U, P
MODE
DRDY
SDOUT
SDIO
+5V
+5V
VOH
C1
6pF
DSYNC
XIN
VOH
0V
P1
2kΩ
XTAL
XOUT
SCLK
DVDD
C2
6pF
DGND
+5V
0
DGND
0
1
2
3
4
5
DGND
V
OH (V)
FIGURE 34. Source Current vs VOH for SDOUT Under Worst-Case Conditions.
SINK CURRENT
30
AIN3N
A
IN3P
+5V
AIN2P
AIN2N
AIN1P
AIN1N
AGND
VBIAS
CS
AIN4N
AIN4P
REFIN
REFOUT
AVDD
25°C
–40°C
R1
49.9kΩ
25
20
15
10
5
85°C
REF1004
+2.5V
1.0µF
0V
AVDD
+5V
ADS1213U, P
MODE
DRDY
SDOUT
SDIO
SCLK
DVDD
+5V
C1
+5V
DSYNC
XIN
VOL
6pF
VOL
0V
P1
2kΩ
XTAL
XOUT
DGND
C2
+5V
0
DGND
6pF
0
1
2
3
4
5
DGND
V
OL (V)
FIGURE 35. Sink Current vs VOL for SDOUT Under Worst-Case Conditions.
Note that an asynchronous DSYNC input may cause mul-
tiple converters to be different from one another by one XIN
clock cycle. This should not be a concern for most applica-
tions. However, the Timing section contains information on
exactly synchronizing multiple converters to the same XIN
clock cycle.
voltage is 5V and the output format is Offset Binary
(FFFFFFH). For sink current, the worst-case condition oc-
curs when the analog input differential voltage is 0V and the
output format is Two’s Complement (000000H).
Note that SDOUT is tri-stated for the majority of the
conversion period and the opto-isolator connection must
take this into account.
tDATA
Synchronization of Multiple Converters
DRDY A
The DSYNC input is used to synchronize the output data of
multiple ADS1212/13s. Synchronization involves configur-
ing each ADS1212/13 to the same Decimation Ratio and
Turbo Mode setting, and providing a common signal to the
XIN inputs. Then, the DSYNC signal is pulsed LOW (see
Figure 22 in the Timing section). This results in an internal
reset of the modulator count for the current conversion.
Thus, all the converters start counting from zero at the same
time, producing a DRDY LOW signal at approximately the
same point (see Figure 36).
tDATA
DRDY B
tDATA
DRDY C
DSYNC
tDATA
FIGURE 36. Affect of Synchronization on Output Data
Timing.
®
34
ADS1212, 1213
BB [ BURR-BROWN CORPORATION ]
