ADS1211 SIMPLIFIED BLOCK DIAGRAM
AGND
6
AV
DD
19
REF
OUT
20
+2.5V
Reference
REF
IN
21
V
BIAS
7
+3.3V Bias
Generator
X
IN
10
X
OUT
11
Clock Generator
12
13
Micro Controller
MUX
Second-Order
∆∑
Modulator
Third-Order
Digital Filter
Instruction Register
Command Register
Data Output Register
Offset Register
Full-Scale Register
14
15
16
17
DRDY
SCLK
SDIO
SDOUT
DGND
DV
DD
A
IN
1P
A
IN
1N
A
IN
2P
A
IN
2N
A
IN
3P
A
IN
3N
A
IN
4P
A
IN
4N
4
5
2
3
24
1
22
23
PGA
Modulator Control
Serial Interface
9
DSYNC
8
CS
18
MODE
ADS1211P AND ADS1211U PIN CONFIGURATION
TOP VIEW
DIP/SOIC
ADS1211P AND ADS1211U PIN DEFINITIONS
PIN NO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
NAME
A
IN
3N
A
IN
2P
A
IN
2N
A
IN
1P
A
IN
1N
AGND
V
BIAS
CS
DSYNC
X
IN
X
OUT
DGND
DV
DD
SCLK
SDIO
SDOUT
DRDY
MODE
AV
DD
REF
OUT
REF
IN
A
IN
4P
A
IN
4N
A
IN
3P
DESCRIPTION
Inverting Input Channel 3.
Noninverting Input Channel 2.
Inverting Input Channel 2.
Noninverting Input Channel 1.
Inverting Input Channel 1.
Analog Ground.
Bias Voltage Output, +3.3V nominal.
Chip Select Input.
Control Input to Synchronize Serial Output Data.
System Clock Input.
System Clock Output (for Crystal or Resonator).
Digital Ground.
Digital Supply, +5V nominal.
Clock Input/Output for serial data transfer.
Serial Data Input (can also function as Serial Data
Output).
Serial Data Output.
Data Ready.
SCLK Control Input (Master = 1, Slave = 0).
Analog Supply, +5V nominal.
Reference Output: +2.5V nominal.
Reference Input.
Noninverting Input Channel 4.
Inverting Input Channel 4.
Noninverting Input Channel 3.
A
IN
3N
A
IN
2P
A
IN
2N
A
IN
1P
A
IN
1N
AGND
V
BIAS
CS
DSYNC
1
2
3
4
5
6
7
8
9
ADS1211P
ADS1211U
24 A
IN
3P
23 A
IN
4N
22 A
IN
4P
21 REF
IN
20 REF
OUT
19 AV
DD
18 MODE
17 DRDY
16 SDOUT
15 SDIO
14 SCLK
13 DV
DD
X
IN
10
X
OUT
11
DGND 12
®
5
ADS1210, 1211