FIGURE INDEX
TABLE INDEX
FIGURE TITLE
PAGE
TABLE
TITLE
PAGE
Figure 1
Figure 2
Figure 3
Figure 4
Normalized Digital Filter Response ......................................... 11
Digital Filter Response at a Data Rate of 50Hz ..................... 11
Digital Filter Response at a Data Rate of 60Hz ..................... 11
Table I
Full-Scale Range vs PGA Setting ............................................. 9
Available PGA Settings vs Turbo Mode Rate .......................... 9
Effective Resolution vs Data Rate and Gain Setting ............. 10
Effective Resolution cs Data Rate and Turbo Mode Rate ..... 12
Noise Level vs Data Rate and Turbo Mode Rate .................. 12
Table II
Table III
Table IV
Table V
Table VI
Asynchronous ADS1210/11 Analog Input Voltage Step or
ADS1211 Channel Change to Fully Settled Output Data ...... 12
Self-Calibration Timing ............................................................ 14
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Effective Resolution vs Data Rate, Clock Frequency, and
System Offset Calibration Timing ........................................... 14
System Full-Scale Calibration ................................................. 14
Pseudo System Calibration Timing ......................................... 15
Background Calibration ........................................................... 15
Turbo Mode Rate .................................................................... 12
Table VII ADS1210/11 Registers ............................................................ 18
Table VIII Instruction Register .................................................................. 19
Table IX
Table X
Table XI
A3-A0 Addressing .................................................................... 19
Organization of the Command Register and Default Status .. 19
Decimation Ratios vs Data Rates ........................................... 21
Figure 10 Sleep Mode to Normal Mode Timing ...................................... 17
Figure 11 Analog Input Structure............................................................. 17
Figure 12 ±10V Input Configuration Using VBIAS .................................................... 18
Figure 13 XIN Clock Timing ...................................................................... 22
Figure 14 Serial Input/Output Timing, Master Mode ............................... 22
Figure 15 Serial Input/Output Timing, Slave Mode ................................. 22
Figure 16 Serial Interface Timing (CS LOW), Master Mode................... 24
Figure 17 Serial Interface Timing (CS LOW), Slave Mode..................... 24
Figure 18 Serial Interface Timing (Using CS), Master Mode.................. 24
Figure 19 Serial Interface Timing (Using CS), Slave Mode.................... 25
Figure 20 SDIO Input to Output Transition Timing ................................. 25
Figure 21 DRDY Rise and Fall Time....................................................... 25
Table XII Data Output Register............................................................... 21
Table XIII Offset Calibration Register ...................................................... 22
Table XIV Full-Scale Calibration Register ................................................ 22
Table XV Digital Timing Characteristics .................................................. 23
Figure 22 DSYNC to XIN Timing for Synchronizing Multiple
ADS1210/11s ........................................................................... 26
Figure 23 Exactly Synchronizing Multiple ADS1210/11s
to Asynchronous DSYNC Signal ............................................. 26
Figure 24 Timing of Data Output Register Update ................................. 26
Figure 25 Flowchart for Writing and Reading Register Data, Master Mode 27
Figure 26 Flowchart for Writing and Reading Register Data, Slave Mode .. 28
Figure 27 Resetting the ADS1210/11 (Slave Mode Only) ...................... 30
Figure 28 Three-Wire Interface with an 8xC32 Microprocessor ............. 31
Figure 29 Three-Wire Interface with an 8xC51 Microprocessor ............. 31
Figure 30 Four-Wire Interface with an 8xC32 Microprocessor ............... 32
Figure 31 Full Interface with an 8xC51 Microprocessor ......................... 32
Figure 32 Full Interface with a 68HC11 Microprocessor ........................ 33
Figure 33 Isolated Four-Wire Interface .................................................... 33
Figure 34 Source Current vs VOH for SDOUT Under
Worst-Case Conditions ............................................................ 34
Figure 35 Sink Current vs VOL for SDOUT Under
Worst-Case Conditions ............................................................ 34
Figure 36 Effect of Synchronization on Output Data Timing .................. 34
Figure 37 Bridge Transducer Interface with Voltage Excitation .............. 36
Figure 38 Bridge Transducer Interface with Current Excitation .............. 36
Figure 39 PT100 Interface ....................................................................... 37
Figure 40 Complete 4-20mA Receiver .................................................... 37
Figure 41 Single Supply, High-Accuracy Thermocouple ......................... 37
Figure 42 Dual Supply, High-Accuracy Thermocouple ........................... 38
Figure 43 Single Supply, High-Accuracy Thermocouple Interface
with Cold Junction Compensation ........................................... 38
Figure 44 Dual Supply, High-Accuracy Thermocouple Interface
with Cold Junction Compensation ........................................... 39
Figure 45 Low-Cost Bridge Transducer Interface with Current Excitation ..... 39
ADS1210, ADS1211
41
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