LAYOUT
POWER SUPPLIES
For a single converter system, AGND and DGND of the
ADS1210/11 should be connected together, underneath the
converter. Do not join the ground planes, but connect the
two with a moderate signal trace. For multiple converters,
connect the two ground planes at one location as central to
all of the converters as possible. In some cases, experimen-
tation may be required to find the best point to connect the
two planes together. The printed circuit board can be de-
signed to provide different analog/digital ground connec-
tions via short jumpers. The initial prototype can be used to
establish which connection works best.
The ADS1210/11 requires the digital supply (DVDD) to be
no greater than the analog supply (AVDD) +0.3V. In the
majority of systems, this means that the analog supply must
come up first, followed by the digital supply. Failure to
observe this condition could cause permanent damage to the
ADS1210/11.
Inputs to the ADS1210/11, such as SDIO, AIN, or REFIN,
should not be present before the analog and digital supplies
are on. Violating this condition could cause latch-up. If these
signals are present before the supplies are on, series resistors
should be used to limit the input current (see the Analog
Input and VBIAS sections of this data sheet for more details
concerning these inputs).
DECOUPLING
Good decoupling practices should be used for the ADS1210/
11 and for all components in the design. All decoupling
capacitors, but specifically the 0.1µF ceramic capacitors,
should be placed as close as possible to the pin being
decoupled. A 1µF to 10µF capacitor, in parallel with a 0.1µF
ceramic capacitor, should be used to decouple AVDD to
AGND. At a minimum, a 0.1µF ceramic capacitor should be
used to decouple DVDD to DGND, as well as for the digital
supply on each digital component.
The best scheme is to power the analog section of the design
and AVDD of the ADS1210/11 from one +5V supply and the
digital section (and DVDD) from a separate +5V supply. The
analog supply should come up first. This will ensure that AIN
and REFIN do not exceed AVDD and that the digital inputs
are present only after AVDD has been established, and that
they do not exceed DVDD
.
The analog supply should be well-regulated and low-noise. For
designs requiring very high resolution from the ADS1210/11,
power supply rejection will be a concern. See the PSRR vs
Frequency curve in the Typical Performance Curves section of
this data sheet for more information.
SYSTEM CONSIDERATIONS
The recommendations for power supplies and grounding
will change depending on the requirements and specific
design of the overall system. Achieving 20 bits or more of
effective resolution is a great deal more difficult than achiev-
ing 12 bits. In general, a system can be broken up into four
different stages:
The requirements for the digital supply are not as strict.
However, high frequency noise on DVDD can capacitively
couple into the analog portion of the ADS1210/11. This
noise can originate from switching power supplies, very fast
microprocessors or digital signal processors.
Analog Processing
Analog Portion of the ADS1210/11
Digital Portion of the ADS1210/11
Digital Processing
For either supply, high frequency noise will generally be
rejected by the digital filter except at interger multiplies of
fMOD. Just below and above these frequencies, noise will
alias back into the passband of the digital filter, affecting the
conversion result.
For the simplest system consisting of minimal analog signal
processing (basic filtering and gain), a self-contained micro-
controller, and one clock source, high-resolution could be
achieved by powering all components by a common power
supply. In addition, all components could share a common
ground plane. Thus, there would be no distinctions between
“analog” and “digital” power and ground. The layout should
still include a power plane, a ground plane, and careful
decoupling.
If one supply must be used to power the ADS1210/11, the
AVDD supply should be used to power DVDD. This connec-
tion can be made via a 10Ω resistor which, along with the
decoupling capacitors, will provide some filtering between
DVDD and AVDD. In some systems, a direct connection can
be made. Experimentation may be the best way to determine
the appropriate connection between AVDD and DVDD
.
In a more extreme case, the design could include: multiple
ADS1210/11s; extensive analog signal processing; one or
more microcontrollers, digital signal processors, or micro-
processors; many different clock sources; and interconnec-
tions to various other systems. High resolution will be very
difficult to achieve for this design. The approach would be
to break the system into as many different parts as possible.
For example, each ADS1210/11 may have its own “analog”
processing front end, its own analog power and ground
(possibly shared with the analog front end), and its own
“digital” power and ground. The converter’s “digital” power
and ground would be separate from the power and ground
for the system’s processors, RAM, ROM, and “glue” logic.
GROUNDING
The analog and digital sections of the design should be care-
fully and cleanly partitioned. Each section should have its own
ground plane with no overlap between them. AGND should be
connected to the analog ground plane as well as all other analog
grounds. DGND should be connected to the digital ground
plane and all digital signals referenced to this plane.
The ADS1210/11 pinout is such that the converter is cleanly
separated into an analog and digital portion. This should allow
simple layout of the analog and digital sections of the design.
ADS1210, ADS1211
35
SBAS034B
www.ti.com
BB [ BURR-BROWN CORPORATION ]
