1-Bit Data
Stream
Switched
Capacitor
Analog
Processor
for
Filtering
2nd-Order
Charge-Balancing
A/D Converter
Input
Analog
Inputs
Programmable Gain Amp
2nd-Order Modulator
V
+
IN
V
REF
1-Bit DAC
V
–
IN
FIGURE 2. Block Diagram of the ADS1201.
ANALOG INPUT STAGE
out of the analog inputs exceed 10mA. In addition, the
linearity of the device is guaranteed only when the analog
voltage applied to either input resides within the range
defined by AGND = > –30mV and < = AVDD + 30mV. If
either of the inputs exceed these limits, the input protection
diodes on the front end of the converter will begin to turn on.
This will induce leakage paths resulting in nonlinearities in
the conversion process.
Analog Input
The input design topology of the ADS1201 is based on a
fully differential switched capacitor architecture. This input
stage provides the mechanism to achieve low system noise,
high common-mode rejection (100dB) and excellent power
supply rejection. The input impedance of the analog input is
dependent on the input capacitor and modulator clock fre-
quency (MCLK), which is also the sampling frequency of
the converter. Figure 3 shows the basic input structure of the
ADS1201. The relationship between the input impedance of
the ADS1201 and the modulator clock frequency is:
For this reason, the 0V to 5V input range must be used with
caution. Should AVDD be 4.75V, the analog input signal
would swing outside the guaranteed specifications of the
device. Designs utilizing this mode of operation should
consider limiting the span to a slightly smaller range. Com-
mon-mode voltages are also a significant concern and must
be carefully analyzed.
1E12
AIN Input Impedance(Ω) =
12 • fMCLK
The input impedance becomes a consideration in designs
where the source impedance of the input signal is signifi-
cant. In this case, it is possible for a portion of the signal to
be lost across this external source impedance. The impor-
tance of this effect depends on the desired system perfor-
mance.
Modulator
The modulator sampling frequency (MCLK) can be oper-
ated over a range of 20kHz to 1MHz. The frequency of
MCLK can be increased to improve the performance of the
converter or adjusted to comply with the clock requirements
of the application.
There are two restrictions on the analog input signal to the
ADS1201. Under no conditions should the current into or
The modulator topology is fundamentally a 2nd-order, charge-
balancing A/D converter, as the one conceptualized in Fig-
ure 4. The analog input voltage and the output of the 1-bit
DAC is differentiated, providing an analog voltage at X2 and
X3. The voltage at X2 and X3 are presented to their indi-
vidual integrators. The output of these integrators progress
in a negative or positive direction. When the value of the
signal at X4 equals the comparator reference voltage, the
output of the comparator switches from negative to positive
or positive to negative, depending on its original state. When
the output value of the comparator switches from a HIGH to
LOW or vise versa, the 1-bit DAC responds on the next
clock pulse by changing its analog output voltage at X6,
causing the integrators to progress in the opposite direction.
The feedback of the modulator to the front end of the
integrators force the value of the integrator output to track
the average of the input.
RSW
8kΩ (typ)
High
Impedance
> 1GΩ
AIN+
CINT
12pF (typ)
VCM
Switching Frequency
= MCLK
CINT
12pF (typ)
RSW
8kΩ (typ)
High
Impedance
AIN–
> 1GΩ
FIGURE 3. Input Impedance of the ADS1201.
®
ADS1201
6
BB [ BURR-BROWN CORPORATION ]
