1
9
1
9
SCL
SDA
…
…
1
0
0
1
A2
A1
A0 R/W
D15 D14 D13 D12 D11 D10 D9
D8
Start By
Master
ACK By
ADS1100
From
ADS1100
ACK By
Master
Frame 1: I2C Slave Address Byte
Frame 2: Output Register Upper Byte
1
9
1
9
SCL
(Continued)
…
…
SDA
(Continued)
ST/
BSY
D7 D6
D5
D4
D3
D2
D1
D0
PGA1 PGA0
SC DR1 DR0
0
0
From
ADS1100
ACK By
Master
ACK By
Master
Stop By
Master
From
ADS1100
Frame 3: Output Register Lower Byte
Frame 4: Configuration Register
(Optional)
FIGURE 2. Timing Diagram for Reading From the ADS1100.
1
9
1
9
SCL
ST/
BSY
A2
PGA1 PGA0
SC DR1 DR0
SDA
1
0
0
1
A1
A0 R/W
0
0
Stop By
Master
Start By
Master
ACK By
ACK By
ADS1100
ADS1100
Frame 1: I2C Slave Address Byte
Frame 2: Configuration Register
FIGURE 3. Timing Diagram for Writing to the ADS1100.
ADS1100
SBAS239B
11
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