TYPICAL CHARACTERISTICS (Cont.)
At TA = 25°C and VDD = 5V, unless otherwise noted.
DATA RATE vs TEMPERATURE
10
FREQUENCY RESPONSE
0
–20
Data Rate = 8SPS
VDD = 2.7V
9
–40
8
–60
VDD = 5V
7
–80
Data Rate = 8SPS
6
–100
0.1
1
10
100
1k
–60 –40 –20
0
20
40
60
80 100 120 140
Input Frequency (Hz)
Temperature (°C)
For a minimum output code of Min Code, gain setting of
PGA, positive and negative input voltages of VIN+ and VIN–
and power supply of VDD, the output code is given by the
expression:
THEORY OF OPERATION
,
The ADS1100 is a fully differential, 16-bit, self-calibrating,
delta-sigma A/D converter. Extremely easy to design with
and configure, the ADS1100 allows you to obtain precise
measurements with a minimum of effort.
V
– V
IN
–
(
)
(
)
IN
+
Output Code = –1•Min Code •PGA •
VDD
The ADS1100 consists of a delta-sigma A/D converter core with
adjustable gain, a clock generator, and an I2C interface. Each of
these blocks are described in detail in the sections that follow.
In the previous expression, it is important to note that the negated
minimum output code is used. The ADS1100 outputs codes in
binary two’s complement format, so the absolute values of the
minima and maxima are not the same; the maximum n-bit code
ANALOG-TO-DIGITAL CONVERTER
is 2n-1 – 1, while the minimum n-bit code is –1 • 2n-1
.
The ADS1100 A/D converter core consists of a differential
switched-capacitor delta-sigma modulator followed by a digital
filter. The modulator measures the voltage difference between
the positive and negative analog inputs and compares it to a
reference voltage, which, in the ADS1100, is the power
supply. The digital filter receives a high-speed bitstream from
the modulator and outputs a code, which is a number
proportional to the input voltage.
For example, the ideal expression for output codes with a
data rate of 16SPS and PGA = 2 is:
V
– V
IN
–
(
)
(
)
IN
+
Output Code = 16384 • 2 •
VDD
The ADS1100 outputs all codes right-justified and sign-
extended. This makes it possible to perform averaging on the
higher data rate codes using only a 16-bit accumulator.
OUTPUT CODE CALCULATION
The output code is a scalar value that is (except for clipping)
proportional to the voltage difference between the two analog
inputs. The output code is confined to a finite range of numbers;
this range depends on the number of bits needed to represent the
code. The number of bits needed to represent the output code for
the ADS1100 depends on the data rate, as shown in Table I.
See Table II for output codes for various input levels.
SELF-CALIBRATION
The previous expressions for the ADS1100’s output code do
not account for the gain and offset errors in the modulator. To
compensate for these, the ADS1100 incorporates self-cali-
bration circuitry.
DATA RATE NUMBER OF BITS MINIMUM CODE MAXIMUM CODE
The self-calibration system operates continuously, and re-
quires no user intervention. No adjustments can be made to
the self-calibration system, and none need to be made. The
self-calibration system cannot be deactivated.
8SPS
16SPS
32SPS
128SPS
16
15
14
12
–32,768
–16,384
–8192
32,767
16,383
8191
–2048
2047
The offset and gain error figures shown in the Electrical
Characteristics include the effects of calibration.
TABLE I. Minimum and Maximum Codes.
ADS1100
6
SBAS239B
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