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ADC574AKH 参数 Datasheet PDF下载

ADC574AKH图片预览
型号: ADC574AKH
PDF下载: 下载PDF文件 查看货源
内容描述: 微处理器兼容模拟数字转换器 [Microprocessor-Compatible ANALOG-TO-DIGITAL CONVERTER]
分类和应用: 转换器微处理器
文件页数/大小: 10 页 / 106 K
品牌: BB [ BURR-BROWN CORPORATION ]
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CE  
CS  
R/C  
12/8  
AO  
OPERATION  
None  
tHRL  
0
X
X
1
0
0
X
X
0
0
0
0
X
X
X
X
X
X
X
X
1
X
X
0
1
0
1
0
1
X
0
1
R/C  
None  
Initiate 12-bit conversion  
Initiate 8-bit conversion  
Initiate 12-bit conversion  
Initiate 8-bit conversion  
Initiate 12-bit conversion  
Initiate 8-bit conversion  
Enable 12-bit output  
Enable 8 MSBs only  
Enable 4 LSBs plus  
4 trailing zeros  
tDS  
1
1
1
1
1
1
1
Status  
0
0
0
0
0
tC  
tHS  
tHDR  
High-Z State  
1
1
1
DB11-DB0  
Data Valid  
Data Valid  
0
0
FIGURE 4. R/C Pulse Low—Outputs Enabled After Con-  
version.  
TABLE III. Control Input Truth Table.  
STAND-ALONE OPERATION  
For stand-alone operation, control of the converter is accom-  
plished by a single control line connected to R/C. In this  
mode CS and AO are connected to digital common and CE  
and 12/8 are connected to VLOGIC (+5V). The output data are  
presented as 12-bit words. The stand-alone mode is used in  
systems containing dedicated input ports which do not  
require full bus interface capability.  
R/C  
tHRH  
tDS  
Status  
tC  
High-Z State  
tHDR  
tDDR  
High-Z  
DB11–  
DB0  
Data Valid  
Conversion is initiated by a high-to-low transition of R/C.  
The three-state data output buffers are enabled when R/C is  
high and STATUS is low. Thus, there are two possible  
modes of operation; conversion can be initiated with either  
positive or negative pulses. In either case the R/C pulse must  
remain low for a minimum of 50ns.  
FIGURE 5. R/C Pulse High—Outputs Enabled Only While  
R/C Is High.  
an 8-bit conversion, the 3LSBs (DB0-DB2) will be low  
(logic 0) and DB3 will be high (logic 1). AO is latched  
because it is also involved in enabling the output buffers. No  
other control inputs are latched.  
Figure 4 illustrates timing when conversion is initiated by an  
R/C pulse which goes low and returns to the high state  
during the conversion. In this case, the three-state outputs  
go to the high-impedance state in response to the falling  
edge of R/C and are enabled for external access of the data  
after completion of the conversion. Figure 5 illustrates the  
timing when conversion is initiated by a positive R/C pulse.  
In this mode the output data from the previous conversion is  
enabled during the positive portion of R/C. A new conver-  
sion is started on the falling edge of R/C, and the three-state  
outputs return to the high-impedance state until the next  
occurrence of a high R/C pulse. Table IV lists timing  
specifications for stand-alone operation.  
CONVERSION START  
The converter is commanded to initiate a conversion by a  
transition occurring on any of three logic inputs (CE, CS,  
and R/C) as shown in Table III. Conversion is initiated by  
the last of the three to reach the required state and thus all  
three may be dynamically controlled. If necessary, all three  
may change states simultaneously, and the nominal delay  
time is the same regardless of which input actually starts  
conversion. If it is desired that a particular input establish the  
actual start of conversion, the other two should be stable a  
minimum of 50ns prior to the transition of that input. Timing  
relationships for start of conversion timing are illustrated in  
Figure 6. The specifications for timing are contained in  
Table V.  
SYMBOL  
PARAMETER  
MIN  
TYP MAX UNITS  
tHRL  
tDS  
tHDR  
tHS  
tHRH  
tDDR  
Low R/C Pulse Width  
STS Delay from R/C  
Data Valid After R/C Low  
STS Delay After Data Valid  
High R/C Pulse Width  
Data Access Time  
50  
ns  
200  
1000  
150  
ns  
ns  
ns  
ns  
ns  
25  
300  
150  
400  
The STATUS output indicates the current state of the con-  
verter by being in a high state only during conversion.  
During this time the three state output buffers remain in a  
high-impedance state, and therefore data cannot be read  
during conversion. During this period additional transitions  
of the three digital inputs which control conversion will be  
ignored, so that conversion cannot be prematurely termi-  
nated or restarted. However, if AO changes state after the  
beginning of conversion, any additional start conversion  
transition will latch the new state of AO, possibly resulting  
in an incorrect conversion length (8 bits vs 12 bits) for that  
conversion.  
TABLE IV. Stand-Alone Mode Timing.  
FULLY CONTROLLED OPERATION  
Conversion Length  
Conversion length (8-bit or 12-bit) is determined by the state  
of the AO input, which is latched upon receipt of a conver-  
sion start transition (described below). If AO is latched high,  
the conversion continues for 8 bits. The full 12-bit conver-  
sion will occur if AO is low. If all 12 bits are read following  
®
8
ADC574A