SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
Convert Mode
tDSC
tHEC
tSSC
tHSC
tSRC
tHRC
tSAC
tHAC
tC
STS Delay from CE
CE Pulse Width
CS to CE Setup time
CS low during CE high
R/C to CE setup
R/C low during CE high
AO to CE setup
AO valid during CE high
Conversion time, 12-bit cycle
8-bit cycle
60
30
20
20
0
200
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
50
50
50
50
50
0
50
15
10
20
20
20
13
25
17
Read Mode
tDD
Access time from CE
Data valid after CE low
Output float delay
CS to CE setup
R/C to CE setup
75
35
100
0
150
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHD
tHL
tSSR
tSRR
tSAR
tHSR
tHRR
tHAR
tHS
25
50
0
50
0
0
50
300
AO to CE setup
25
CS valid after CE low
R/C high after CE low
AO valid after CE low
STS delay after data valid
400
1000
NOTE: Specifications are at +25°C and measured at 50% level of transitions.
TABLE V. Timing Specifications.
CE
CS
CE
CS
tHEC
tSSR
tHSR
tSSC
tHRR
tSRC
tHSC
R/C
AO
R/C
AO
tSRR
tHRC
tHAR
tSAR
tSAC
STS
tHAC
STS
tHS
tHD
tDSC
tC
High-Z
tDD
DB11–
DB0
Data Valid
High Impedance
DB11–
DB0
tHL
FIGURE 6. Conversion Cycle Timing.
FIGURE 7. Read Cycle Timing.
desired. When 12/8 is high, all 12 output lines (DB0–DB11)
are enabled simultaneously for full data word transfer to a
12-bit or 16-bit bus. In this situation the AO state is ignored.
READING OUTPUT DATA
After conversion is initiated, the output data buffers remain
in a high-impedance state until the following four logic
conditions are simultaneously met: R/C high, STATUS low,
CE high, and CS low. Upon satisfaction of these conditions
the data lines are enabled according to the state of inputs
12/8 and AO. See Figure 7 and Table V for timing relation-
ships and specifications.
When 12/8 is low, the data is presented in the form of two
8-bit bytes, with selection of the byte of interest accom-
plished by the state of AO during the read cycle. Connection
of the ADC574A to an 8-bit bus for transfer of left-justified
data is illustrated in Figure 8. The AO input is usually driven
by the least significant bit of the address bus, allowing
storage of the output data word in two consecutive memory
locations.
In most applications the 12/8 input will be hard-wired in
either the high or low condition, although it is fully TTL-
and CMOS-compatible and may be actively driven if
®
ADC574A
9
BB [ BURR-BROWN CORPORATION ]
