AZP92
SIGNAL DESCRIPTION
PIN/PAD FUNCTION
D
Data Input
Q/Q¯
Data Outputs
VBB/D¯
EN
EN-SEL
DIV-SEL
VEE
Reference Voltage Output
Enable/Reset Input
Enable Logic Select
Divide Ratio Select
Negative Supply
VCC
Positive Supply
ENABLE TRUTH TABLE
EN
CMOS Low or VEE
CMOS High, VCC or NC Data
CMOS Low, VEE or NC
CMOS High or VCC
PECL Low, VEE or NC
PECL High or VCC
DIVIDE TRUTH TABLE
EN-SEL
NC
NC
VEE
VEE
20kΩ to VEE
20kΩ to VEE
Q
Low
Q¯
DIV-SEL
DIVIDE
RATIO
÷1
High
Data
High
Data
Data
High
NC
Low
1
VEE
÷2
Data
Data
Low
1
DIV-SEL connection must
be ≤1Ω.
D
EN (EN-SEL CONNECTED TO
(PECL)
V
EE VIA 20k RESISTOR)
EN (EN-SEL OPEN OR
(CMOS)
CONNECTED TO VEE
)
(DIV-SEL
OPEN)
Q
(DIV-SEL
CONNECTED
Q
TO VEE
)
TIMING DIAGRAM
June 2009 REV - 9
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2
AZM [ ARIZONA MICROTEK, INC ]
