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AZ10LVEL16VST 参数 Datasheet PDF下载

AZ10LVEL16VST图片预览
型号: AZ10LVEL16VST
PDF下载: 下载PDF文件 查看货源
内容描述: ECL / PECL差分接收器与可变输出摆幅 [ECL/PECL Differential Receiver with Variable Output Swing]
分类和应用:
文件页数/大小: 8 页 / 101 K
品牌: AZM [ ARIZONA MICROTEK, INC ]
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ARIZONA MICROTEK, INC.  
AZ10LVEL16VS  
AZ100LVEL16VS  
ECL/PECL Differential Receiver with Variable Output Swing  
FEATURES  
PACKAGE AVAILABILITY  
250ps Propagation Delay  
PACKAGE  
PART NUMBER  
MARKING NOTES  
High Bandwidth Output Transitions  
Operating Range of 3.0V to 5.5V  
Internal Input Pulldown Resistors  
Functionally Equivalent to ON  
Semiconductor MC10EL16,  
MC100EL16 & MC100LVEL16  
Variable Output Swing  
AZM10  
LV16VS  
SOIC 8  
AZ10LVEL16VSD  
1,2  
AZM100  
LV16VS  
SOIC 8  
AZ100LVEL16VSD  
AZ10LVEL16VST  
AZ100LVEL16VST  
1,2  
AZT  
L16VS  
TSSOP 8  
TSSOP 8  
1,2  
AZH  
L16VS  
1,2  
1
2
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)  
Tape & Reel.  
Date code format: “Y” or “YY” for year followed by “WW” for week on  
underside of part.  
DESCRIPTION  
The  
AZ10/100LVEL16VS  
is  
a
differential receiver with variable output swing. The LVEL16VS has functionality and output transition times  
similar to the EL16, with an input that controls the amplitude of the Q/Q¯ outputs.  
The operational range of the LVEL16VS control input, VCTRL, is from VBB (full swing) to VCC (min. swing).  
Maximum swing is achieved by leaving the VCTRL pin open or by tying it to the negative supply (VEE). Simple  
control of the output swing can be obtained by a variable resistor between the VBB and VCC pins, with the wiper  
driving VCTRL. Typical application circuits and results are described in this Data Sheet.  
The LVEL16VS provides a VBB output for single-ended use or a DC bias reference for AC coupling to the  
device. For single-ended input applications, the VBB reference should be connected to one side of the D/D¯  
differential input pair. The input signal is then fed to the other D/D¯ input. The VBB pin can support 1.5mA  
sink/source current. When used, the VBB pin should be bypassed to ground via a 0.01μF capacitor.  
Under open input conditions internal input clamps will force the Q output LOW.  
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.  
PIN DESCRIPTION  
1
2
3
4
8
V
V
CTRL  
CC  
PIN  
D, D¯  
VCTRL  
Q, Q¯  
VBB  
FUNCTION  
Data Inputs  
Output Swing Control  
Data Outputs  
Reference Voltage Output  
Positive Supply  
Negative Supply  
Q
7
6
5
D
D
VCC  
VEE  
Q
V
V
EE  
BB  
LOGIC DIAGRAM AND PINOUT ASSIGNMENT  
1630 S. STAPLEY DR., SUITE 127 MESA, ARIZONA 85204 USA (480) 962-5881 FAX (480) 890-2541  
www.azmicrotek.com