ARIZONA MICROTEK, INC.
AZ10E131
AZ100E131
ECL/PECL 4-bit D Flip-Flop
FEATURES
PACKAGE AVAILABILITY
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1100 MHz Min. Toggle Frequency
Differential Outputs
Individual and Common Clocks
Individual Resets (asynchronous)
Paired Sets (asynchronous)
Operating Range of 4.2V to 5.46V
75kΩ Internal Input Pulldown Resistors
Direct Replacement for On Semiconductor
MC10E131 & MC100E131
PACKAGE
PART NUMBER
MARKING
NOTES
AZM10E131
<Date Code>
AZM100E131
<Date Code>
PLCC 28
AZ10E131FN
1,2
PLCC 28
AZ100E131FN
1,2
1
2
Add R2 at end of part number for 13 inch (2.5K parts) Tape & Reel.
Date code format: “YY” for year followed by “WW” for week.
DESCRIPTION
The AZ10/100E131 is a quad master-slave D-type flip-flop with differential outputs. Each flip-flop may be
clocked separately by holding Common Clock (CC) LOW and using the Clock Enable (C¯¯En) inputs for clocking.
Common clocking is achieved by holding the C¯¯En inputs LOW and using CC to clock all four flip-flops. In this
case, the C¯¯En inputs perform the function of controlling the common clock to each flip-flop.
Individual asynchronous resets are provided (Rn). Asynchronous set controls (Sn) are ganged together in pairs,
with the pairing chosen to reflect physical chip symmetry.
Data enters the master when both CC and C¯¯En are LOW, and transfers to the slave when either CC or C¯¯En (or
both) go HIGH.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
R3
25
D2
24
CE2
23
R2
22
VCCO
Q3
20
Q3
19
21
18
17
Q2
Q2
CE3
D3
26
27
VCC
Q1
28
1
16
15
S12
VEE
CC
Pinout: 28-Lead
PLCC (top view)
Q1
14
2
Q0
Q0
3
13
12
S03
D0
4
5
6
7
8
9
10
11
CE0
R0
D1
CE1
R1
NC
VCCO
* All VCC and VCCO pins are tied together on the die.
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541
www.azmicrotek.com
AZM [ ARIZONA MICROTEK, INC ]
